Technical Library | 2023-01-17 17:12:33.0
Reflowed indium metal has for decades been the standard for solder thermal interface materials (solder TIMs or sTIMs) in most high-performance computing (HPC) TIM1 applications. The IEEE Heterogeneous Integration Thermal roadmap states that new thermal interface materials solutions must provide a path to the successful application of increased total-package die areas up to 100cm2. While GPU architectures are relatively isothermal during usage, CPU hotspots in complex heterogeneously-integrated modules will need to be able to handle heat flux hotspots up to 1000W/cm2 within the next two years. Indium and its alloys are used as reflowed solder thermal interface materials in both CPU and GPU "die to lid/heat spreader" (TIM1) applications. Their high bulk thermal conductivity and proven long-term reliability suit them well for extreme thermomechanical stresses. Voiding is the most important failure mode and has been studied by x-ray. The effects of surface pretreatment, pressure during reflow, solder flux type/fluxless processing, and preform design parameters, such as alloy type, are also examined. The paper includes data on both vacuum and pressure (autoclave) reflow of sTIMs, which is becoming necessary to meet upcoming requirements for ultralow voiding in some instances.
Technical Library | 2010-01-13 12:34:10.0
Micro-sectioning (sometimes referred to as cross-sectioning)is a technique, used to characterize materials or to perform a failure mode analysis, for exposing an internal section of a PCB or package. Destructive in nature, cross-sectioning requires encapsulation of the specimen in order to provide support, stability, and protection. Failures that can be investigated through micro-sectional analysis include component defects, thermo-mechanical failures, processing failures related to solder reflow, opens or shorts, voiding and raw material evaluations.
Technical Library | 2008-10-23 15:36:58.0
As part of continuous process improvement at KEMET, most failure modes caused by the capacitor manufacturing process have been systematically eliminated. Today these capacitor manufacturing-related defects are now at a parts per billion (PPB) level. Pareto analysis of customer complaints indicates that the #1 failure mode is IR failure due to flex cracks.
Technical Library | 2018-02-07 22:50:31.0
The architecture of vehicle electrical systems is changing rapidly. Electric and hybrid vehicles are driving mixed voltage systems, and cost pressures are making conductor materials like aluminum an increasingly viable competitor to copper. This paper presents tradeoff studies at the vehicle level, and how to automatically generate an electrical Failure Mode Effects and Analysis (FMEA) report, as well as how to optimize wire sizes for both copper and aluminum at the platform level.
Technical Library | 2014-12-11 18:00:09.0
The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Wire bonded packages using conventional copper lead frame have been used in industry for quite some time. However, the demand for consumer electronics is driving the need for flip chip interconnects as these packages shorten the signals, reduce inductance and improve functionality as compared to the wire bonded packages. The flip chip packages have solder bumps as interconnects instead of wire bonds and typically use an interposer or organic substrate instead of a metal lead frame (...) The paper provides a general overview of typical defects and failure modes seen in package assembly and reviews the efforts needed to understand new failure modes during package assembly. The root cause evaluations and lessons learned as the factory transitioned to thin form factor packages are shared
Technical Library | 2017-08-31 13:43:48.0
Wire bonded packages using conventional copper leadframe have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – non-stick on pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction
Technical Library | 2014-08-19 16:04:28.0
SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller, with denser interconnect arrays, and processes such package-on-package assembly become prevalent, advanced methods using dual surface full-field data become critical for effective Assembly Planning, Quality Assurance, and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required, to effectively address the challenges of modern SMT assembly.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2019-07-30 15:29:50.0
Area Array microelectronic packages with small pitch and large I/O counts are now widely used in microelectronics packaging. The impact of various package design and materials/process parameters on reliability has been studied through extensive literature review. Reliability of Ceramic Column Grid Array (CCGA) package assemblies has been evaluated using JPL thermal cycle test results (-50°/75°C, -55°/100°C, and -55°/125°C), as well as those reported by other investigators. A sensitivity analysis has been performed using the literature data to study the impact of design parameters and global/local stress conditions on assembly reliability. The applicability of various life-prediction models for CCGA design has been investigated by comparing model's predictions with the experimental thermal cycling data. Finite Element Method (FEM) analysis has been conducted to assess the state of the stress/strain in CCGA assembly under different thermal cycling, and to explain the different failure modes and locations observed in JPL test assemblies.
Technical Library | 2024-09-02 18:48:58.0
The conversion to higher temperature "Lead Free" assembly reflow conditions has created an increased awareness that entrapped or absorbed moisture is a frequent root cause of thermally induced delamination at assembly reflow. There are two connected failure modes from entrapped moisture; incomplete resin cross-linking resulting in premature resin decomposition and also severe Z axis expansion from "explosive vaporization of the entrapped moisture at elevated temperatures at assembly reflow". Ultimately, both result in delamination failure. Other papers have shown the negative effects of entrapped moisture before lamination including delamination, red color, reduced thermal reliability and increased high speed signal loss. In this paper, various materials were tested for moisture sensitivity during lamination. Tests were performed at varying lamination conditions including a pre-vacuum step and "kiss" step. Pressure and cure temperature parameters were evaluated for minimizing or eliminating the effect of trapped moisture. Also included are the results of inner layer moisture removal baking conditions and their effect on peel strength and thermal reliability.
