Technical Library | 2013-11-21 12:01:11.0
Previous experimentation on a highly miniaturized and densely populated SMT assembly revealed the optimum stencil alloy and flux-repellent coating for its stencil printing process. Production implementation of the materials that were identified in the study resulted in approximately 5% print yield improvement across all assemblies throughout the operation, validating the results of the initial tests. A new set of studies was launched to focus on the materials themselves, with the purpose of optimizing their performance on the assembly line (...) Results of the prior tests are reviewed, and the new test vehicle, experimental setup and results are presented and discussed.
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
Technical Library | 2012-03-15 17:50:28.0
The competition in the EMS sector has considerably intensified over the last few years,. The enormous pressure to reduce production costs, which every service provider today has to face, frequently forces the organization to have a critical look at their
Technical Library | 2006-12-04 16:38:18.0
This paper will explore how test can be an integral part of manufacturing to assure High Reliability Products. We will discuss how test parameters and test techniques are effective in finding time zero vs. time dependent defects. Understanding of manufacturing processes in terms defect levels as well as defect types is very critical in defining test parameters, new test techniques and test alternatives. This ultimately can improve the yield, quality, and reliability. We will discuss the types of defects, time zero vs. time dependent defects, test parameters and effectiveness and new test techniques to find time dependent defects.
Technical Library | 2015-06-11 21:20:29.0
The use of bottom terminated components (BTC) has become widespread, specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type, improved electrical and thermal performance relative to older packaging technology, and low cost make the QFN/BTC attractive for many applications.Over the past 15 years, the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design, and must be given special attention to balance the dissimilar requirements
Technical Library | 2023-05-02 18:54:30.0
Surface-mount PCB components are smaller than their lead-based counterparts and provide a radically higher component density. They are available in a variety of shapes and sizes designated by a series of standardized codes curated by the electronics industry. Of these PCB components, the 0201-sized are the smallest, measuring 0.024 x 0.012 in. (0.6 x 0.3 mm) – that's 70% smaller than the previous 0402 level! The 0201 components are designed to improve reliability in space-constrained applications such as portable electronics like smartphones, tablets, robotics and digital cameras, but require delicate handling during the assembly process.
Technical Library | 2023-09-18 14:10:01.0
As with many advancements in the electronics industry, consumer electronics is driving the trends for electronic packaging technologies toward reducing size and increasing functionality. Microelectronics meeting the technology needs for higher performance, reduced power consumption and size, and off the- shelf availability. Due to the breadth of work being performed in the area of microelectronics packaging/components, this report limits it presentation to board design, manufacturing, and processing parameters on assembly reliability for leadless (e.g., quad flat no-lead (QFN) or a generic term of bottom termination component (BTC)) packages. This style of package was selected for investigation because of its significant growth, lower cost, and improved functionality, especially for use in an RF application.
Technical Library | 2016-01-12 11:01:25.0
More and more Land Grid Array (LGA) components are being used in electronic devices such as smartphones, tablets and computers. In order to enhance LGA mechanical strength and reliability, capillary flow underfill is used to improve reliability. However, due to the small gap, it is difficult for capillary underfill to flow into the LGA at SMT level. Due to cost considerations, there are usually no pre-heating underfill or cleaning flux residue processes at the SMT assembly line. YINCAE solder joint encapsulant SMT256 has been successfully used with solder paste for LGA assembly. Solder joint encapsulant is used in in-line LGA soldering process with enhanced reliability. It eliminates the underfilling process and provides excellent reworkability. The shear st rength of solder joint is stronger than that of underfilled components. The thermal cycling performance using solder joint encapsulant is much better than that using underfill. Bottom IC of POP has been studied for further understanding of LGA assembly process parameters. All details such as assembly process, drop test and thermal cycling test will be discussed in this paper.
Technical Library | 2016-01-12 11:03:35.0
With the pitch size of interconnect getting finer and finer, the bonding strength between flexible and rigid (e.g. PCB, ceramic) substrates becomes a serious issue because it is not strong enough to meet the customer’s requirement. Capillary underfill has been used to enhance the bonding strength between flexible and rigid substrates, but the enhancement is very limited, particularly for high temperature application. The bonding strength of underfilled flexible/rigid interconnect is dramatically decreased after being used at 180◦C, and the interconnects are weakened by the internal stress caused by the expansion of underfill at high temperatures. In order to resolve reliability issues of the interconnect between flexible/rigid substrates, solder joint encapsulant was implemented into the thermal compression bonding process, which was used to manufacture the interconnect between flexible/rigid substrates. Compared to the traditional process, the strength of the interconnect was doubled and the reliability was significantly improved in high temperature application.
Technical Library | 2019-02-27 15:23:47.0
A study was performed to investigate, evaluate and qualify new reworkable underfill materials to be used primarily with ball grid arrays (BGAs), Leadless SMT devices, QFNs, connectors and passive devices to improve reliability. The supplier of the sole source, currently used underfill, has indicated they may discontinue its manufacture in the near future. The current underfill material is used on numerous circuit card assemblies (CCAs) at several sites and across multiple programs/business areas. In addition, it is used by several of our contract CCA suppliers.The study objectives include evaluation of material properties for down select, dispensability and rework evaluation for further down select, accelerated life testing for final selection and qualification; and process development to implement into production and at our CCA suppliers. The paper will describe the approach used, material property test results and general findings relative to process characteristics and rework ability.
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