Technical Library | 2023-01-17 17:22:28.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC- 9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2019-06-19 11:06:46.0
Tin (Sn) metal displays the characteristic of growing “tin whiskers” from pure tin coatings (most actively on relatively thin, electrodeposited or immersion tin coatings), usually months or years from the initial deposition of the tin. Tin whiskers are electrically conductive, filamentary, single crystals of white (beta phase) tin. These filaments of single crystal tin are usually one to five microns in diameter, and a few microns up to several tens of millimeters long, that grow spontaneously from the tin coatings. Alloying additions of several percent (by weight) of lead (Pb) prevents these electrically conductive tin whiskers from growing. Pb alloyed into the Sn was discovered to prevent the occurrence of tin whiskers in electronic assemblies in the 1950s as the Bell Laboratories solution to the problem of tin whiskers. The alloying of the tin with lead has thus quietly averted incalculable losses from short circuits in electronic equipment for the last 60 years.
Technical Library | 2012-08-16 22:38:05.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. The physical mechanisms behind tin whisker formation in pure tin (Sn) films continue to elude the microelectronics industry. Despite modest advances in whisker mitigation techniqu
Technical Library | 2015-06-04 19:10:47.0
Integrators and designers of high-reliability systems exert little or no control over component-level plating processes that affect the propensity for tin whiskering. Challenges of how to assure long-term reliability, while continuing to use COTS parts plated with pure tin, continue to arise. An integrated, quantitative, standardized methodology is proposed whereby mitigation levels can be selected that are appropriate for specific applications of pure tin for given end-uses. A system of hardware end-use classification is proposed, together with recommended appropriate risk mitigation approaches. An updated version of the application-specific risk assessment algorithm is presented together with recommended thresholds for acceptability within the context of the hardware classifications.
Technical Library | 2012-08-02 21:05:14.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. Pure tin is a common finish for copper hook up wire, coaxial cable, ground braid and harness assemblies used on electronic assemblies. Historically there have been fewer reports o
Technical Library | 2023-02-13 19:23:18.0
Spontaneously forming tin whiskers, which emerge unpredictably from pure tin surfaces, have regained prevalence as a topic within the electronics research community. This has resulted from the ROHS-driven conversion to "lead-free" solderable finish processes. Intrinsic stresses (and/or gradients) in plated films are considered to be a primary driving force behind the growth of tin whiskers. This paper compares the formation of tin whiskers on nanocrystalline and conventional polycrystalline copper deposits. Nanocrystalline copper under-metal deposits were investigated, in terms of their ability to mitigate whisker formation, because of their fine grain size and reduced film stress. Pure tin films were deposited using matte and bright electroplating, electroless plating, and electron beam evaporation. The samples were then subjected to thermal cycling conditions in order to expedite whisker growth. The resultant surface morphologies and whisker formations were evaluated.
Technical Library | 2017-10-12 15:45:25.0
The risk associated with whisker growth from pure tin solderable terminations is fully mitigated when all of the pure tin is dissolved into tin-lead solder during SMT reflow. In order to take full advantage of this phenomenon, it is necessary to understand the conditions under which such coverage can be assured. A round robin study has been performed by IPC Task group 8-81f, during which identical sets of test vehicles were assembled at multiple locations, in accordance with IPC J-STD-001, Class 3. All of the test vehicles were analyzed to determine the extent of complete tin dissolution on a variety of component types. Results of this study are presented together with relevant conclusions and recommendations to guide high reliability end-users on the applicability and limitations of this mitigation strategy.
Technical Library | 2014-03-06 19:04:07.0
Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.
Technical Library | 2015-01-05 17:38:26.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC-9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2023-09-26 19:14:44.0
The transition from tin-lead to lead free soldering in the electronics manufacturing industry has been in progress for the past 10 years. In the interim period before lead free assemblies are uniformly accepted, mixed formulation solder joints are becoming commonplace in electronic assemblies. For example, area array components (BGA/CSP) are frequently available only with lead free Sn-Ag-Cu (SAC) solder balls. Such parts are often assembled to printed circuit boards using traditional 63Sn-37Pb solder paste. The resulting solder joints contain unusual quaternary alloys of Sn, Ag, Cu, and Pb. In addition, the alloy composition can vary across the solder joint based on the paste to ball solder volumes and the reflow profile utilized. The mechanical and physical properties of such Sn-Ag-Cu-Pb alloys have not been explored extensively in the literature. In addition, the reliability of mixed formulation solder joints is poorly understood.
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