Technical Library | 1999-05-07 10:38:11.0
This paper is a report of a study made to determine the maximum allowable impurities in solder used for wave soldering applications. This report concludes with a list of impurities compiled from actual analyses of solder which caused production problems. A list of recommended maximum allowable impurities will assist in establishing reliable quality controls on the purity level of the solder in a wave soldering machine.
Technical Library | 2006-12-18 14:55:35.0
Many solder users have preconceived notions and worries involving reflow profiling guidelines. Year after year of reading profiling recommendations in industry publications, from a litany of pundits, has made it clear that perfect profiles exist and should be sought after. They feel if the solder supplier gives them a tidy drawing on a piece of paper with times and temperatures that it will magically solve all their reflow problems. This is, unfortunately, an often incorrect assumption.
Technical Library | 2009-03-25 17:14:11.0
This article presents design guidelines for helping users of HDMI mux-repeaters to maximize the device's full performance through careful printed circuit board (PCB) design. We'll explain important concepts of some main aspects of high-speed PCB design with recommendations. This discussion will cover layer stack, differential traces, controlled impedance transmission lines, discontinuities, routing guidelines, reference planes, vias and decoupling capacitors.
Technical Library | 2012-10-25 16:34:02.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper will examine stencil technologies (including Laser and Electroform), Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings), and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.
Technical Library | 2014-03-13 15:25:01.0
A student competition paper at Budapest University of Technology And Economics, Department of Electronics Technology gives background, covers stencil design and discusses stencils intended for pin in paste application. The stencil applied for depositing the solder paste is a thin, 75–200 µm thick metal foil, on which apertures are formed according to the solder pads on the printed circuit board. Stencil printing provides a fast, mass solder paste deposition process; relatively expensive, appropriate and recommended for mass production.
Technical Library | 2021-09-15 18:58:01.0
Mathematical model for dynamic force analysis of printed circuit boards has been designed to calculate dynamic deformations and stresses in printed circuit boards and assess their dynamic strength and rigidity. The represented model describes a printed circuit board as a separate oscillatory system, which is simulated as prismatic beam set on two oscillating supports. Simulation and assessment of stress and deflection in printed circuit boards and obtaining their amplitude frequency responses provided recommendations, which ensure strength and stiffness of printed circuit boards subjected to dynamic loads..
Technical Library | 2006-10-26 08:08:00.0
There have been many studies of the causes of tombstoning; some published, some not. They tend to focus on a single process parameter as the root cause of tombstoning. However, there is no single process change that is a sure cure for tombstoning! Those that claim otherwise are either uninformed or trying to sell you something. Rather than limiting your view to a single solution, EFD recommends you heed all of the studies. Like pieces of a puzzle, each study does not reveal the whole picture, but looked at all together, the picture is clear.
Technical Library | 2018-10-03 20:41:44.0
Voids in solder joints plague many electronics manufacturers. Do you have voids in your life? We have good news for you, there are many excellent ways to "Fill the Void." This paper is a continuation of previous work on voiding in which the following variables were studied: water soluble lead-free solder pastes, a variety of stencil designs, and reflow profiles. Quad Flat No-Lead (QFN) component thermal pads were used as the test vehicle. The voiding results were summarized and recommendations were made for reduction of voiding.
Technical Library | 2018-11-20 21:33:57.0
There are several industry-accepted methods for determining the reliability of flux residues after assembly. The recommended methods of test sample preparation do not always closely mimic the thermal cycle experienced by an assembly. Therefore, extraction from actual assemblies has become a popular method of process control to assess consistency of post-reflow cleanliness. Every method of post-reflow flux residue characterization will depend on the reflow process followed to prepare the coupon.This investigation will focus on the effect of thermal conditions on the remainder of active ingredients in flux residues after assembly with no-clean solder pastes.
Technical Library | 2021-04-01 14:36:51.0
This document provides information about the Surface Mount Technology (SMT) board assembly of Infineon Thin Small Non-leaded Packages (TSNP). The specific dimensions of the leadframe based inner setup depend on the size of the chip and the type of bonding. The field of application ranges from linear voltage regulators for weight-limited applications such as cellular phones and digital cameras to linear voltage regulators for the automotive sector.
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