Technical Library | 2007-09-27 16:18:15.0
Considerable interest exists in the process known as the pinin- paste, or the Alternative Assembly and Reflow Technology (AART) process. The AART process allows for the simultaneous reflow of both odd-form and through hole devices as well as surface mount components. This process has several advantages over the typical mixed technology process sequence that includes wave soldering and/or hand soldering, often in addition to reflow soldering.
Technical Library | 2013-02-08 22:56:47.0
Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.
Technical Library | 2017-10-16 15:03:32.0
The miniaturization and advancement of electronic devices have been the driving force of design, research and development, and manufacturing in the electronic industry. However, there are some issues occurred associated with the miniaturization, for examples, warpage and reliability issues. In order to resolve these issues, a lot of research and development have been conducted in the industry and university with the target of moderate melting temperature solder alloys such as m.p. 280°C. These moderate temperature alloys have not resolve these issues yet due to the various limitations. YINCAE has been working on research and development of the materials with lower temperature soldering for higher temperature application. To meet this demand, YINCAE has developed solder joint encapsulant paste to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. This solder joint encapsulant paste can be used in typical lead-free profile and after reflow the application temperature can be up to over 300C, therefore it also eliminates red glue for double side reflow process. In this paper, we will discuss the reliability such as strength of solder joints, drop test performance and thermal cycling performance using this solder joint encapsulant paste in detail.
Technical Library | 2010-05-12 16:21:05.0
Numerous studies have shown that greater than 60% of end of line defects in SMT assembly can be traced to solder paste and the printing process. Reflowing adds another 15% or so. In light of this fact, it is surprising that no simplified procedure for solder paste evaluation has been documented. This paper is about such a procedure.
Technical Library | 2007-03-28 10:18:33.0
Legislation against the use of lead in electronics has been the driving force behind the use of lead-free solders, surface finishes, and component lead finishes. The major concern in using lead-free solders in the assembly and rework Chip Scale Packages (CSPs) is the relatively high temperatures that the components and the boards experience. Fine-pitch CSPs have very low standoff heights following assembly making inspection and rework of these components more difficult. One other concern pertinent to rework is the temperature of the neighboring components during rework. These issues, coupled with the limitations of rework equipment to handle lead-free reflow temperatures, make the task of reworking lead-free assemblies more challenging.
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
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