Technical Library | 2007-04-05 13:48:50.0
Recently a large global player approached us with a problem. They needed an initial assembly solution for brand new components. Their boards and CSP specimens could not safely be soldered due to wetting problems at the solder joints.
Technical Library | 2013-03-04 16:51:00.0
Chip-scale (or chip-size) packages are rapidly becoming an important element in electronics due to their size, performance, and cost advantages [Hou, 1998]. The Chip Scale Package (CSP) is becoming a key semiconductor package type, particularly for consumer products. Due to their relatively smaller size, new challenges are presented in the rework and repair of CSPs. (...) The specific focus of this paper is the removal process for rework of CSPs and the site scavenging methods required to properly prepare the circuit board for a new component. Process factors such as the heating, fluxing and, atmosphere are discussed.
Technical Library | 2021-04-15 14:44:20.0
Automated inspection of surface mount PCB boards is a requirement to assure quality and to reduce manufacturing scrap costs and rework. This paper investigates methodologies for locating and identifying multiple objects in images used for surface mount device inspection. One of the main challenges for surface mount device inspection is component placement inspection.
Technical Library | 2014-04-11 16:03:15.0
In order to meet the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, underfilling has increasingly become an essential process for the good reliability of electronic devices. Filled capillary underfill has been selected for use in package-level where there is large thermal stress caused by CTE mismatch issue, but the underfill is usually not reworkable. Unfilled capillary underfill has been used for board-level application such as BGA/CSP, POP, WL-CSP where there is need for mechanical shock resistance, the underfill is usually reworkable.
Technical Library | 2016-01-12 11:09:47.0
In order to meet the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, underfilling has increasingly become an essential process for the good reliability of electronic devices. Filled capillary underfill has been selected for used in package-level where there is large thermal stress caused by CTE mismatch issue, but the underfill is usually not reworkable. Unfilled capillary underfill has been used for board-level application such as BGA/CSP, POP, WL-CSP where there is need for mechanical shock resistance, the underfill is usually reworkable.
Technical Library | 2016-10-03 08:28:47.0
With the miniaturization of electronic device, Land Grid Array (LGA) or QFN has been widely used in consumer electronic products. However there is only 20-30 microns gap left between LGA and the substrate, it is very difficult for capillary underfill to flow into the large LGA component at room temperature. Insufficient underfilling will lead to the loss of quality control and the poor reliability issue. In order to resolve these issues, a room temperature fast flow reworkable underfill has been successfully developed with excellent flowability. The underfill can flow into 20 microns gap and complete the flow of 15mm distance for about 30 seconds at room temperature. The curing behavior, storage, thermal cycling performance and reworkability will be discussed in details in this paper.
Technical Library | 2024-01-15 20:45:42.0
Miniaturization continues to be a driving force in both integrated circuit packaging and printed circuit board laminate technology. In addition to decreasing component pitch (lead to lead spacing), utilization of the vertical space by stacking packages has found wide acceptance by both designers and manufactures of electronics alike. Lead free Package on Package (PoP) technology represents one of the latest advancements in vertical electronics packaging integration and has become the preferred technology for mobile hand held electronics applications. TT Electronics in Perry, Ohio has developed the capability to assemble and rework numerous "state of the art" packaging technologies. This paper will focus on the essential engineering development activities performed to demonstrate TT Electronics' ability to both assemble and rework PoP components.
Technical Library | 2024-01-16 22:29:59.0
Miniaturization continues to be a driving force in both integrated circuit packaging and printed circuit board laminate technology. In addition to decreasing component pitch (lead to lead spacing), utilization of the vertical space by stacking packages has found wide acceptance by both designers and manufactures of electronics alike. Lead free Package on Package (PoP) technology represents one of the latest advancements in vertical electronics packaging integration and has become the preferred technology for mobile hand held electronics applications. TT Electronics in Perry, Ohio has developed the capability to assemble and rework numerous "state of the art" packaging technologies. This paper will focus on the essential engineering development activities performed to demonstrate TT Electronics' ability to both assemble and rework PoP components.
Technical Library | 1999-05-09 12:51:38.0
This Technical Note outlines, step by step, the easiest ways to remove and replace surface mounted devices, using the lowest possible temperatures. This document discusses the following topics: Removal and replacement of discrete and passive components (capacitors, resistors, SOTs), Removal of two-sided components (SOICs, SOJs, TSOPs), Removal of quad components (PLCCs, QFPs), Replacement of quad components including fine-pitched devices.
Technical Library | 2012-03-22 20:40:01.0
Miniaturization continues to be a driving force in both integrated circuit packaging and printed circuit board laminate technology. In addition to decreasing component pitch (lead to lead spacing), utilization of the vertical space by stacking packages ha
