Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 2024-06-19 13:59:50.0
The solderability of a nickel-palladium-gold (Ni-Pd-Au) finish on a Cu substrate was evaluated for the Pb-free solder, 95.5Sn-3.9Ag-0.6 Cu (wt.%, abbreviated Sn-Ag-Cu) and the eutectic 63Sn-37 Pb (Sn-Pb) alloy. The solder temperature was 245ºC. The flux was a rosin-based mildly activated (RMA) solution. The Ni-Pd-Au finish was tested in the as-fabricated condition as well as after exposure to one of the following accelerated storage (shelf life) regiments:
Technical Library | 2022-03-02 21:26:51.0
The solderability of a nickel-palladium-gold (Ni-Pd-Au) finish on a Cu substrate was evaluated for the Pb-free solder, 95.5Sn-3.9Ag-0.6 Cu (wt.%, abbreviated Sn-Ag-Cu) and the eutectic 63Sn-37 Pb (Sn-Pb) alloy. The solder temperature was 245ºC. The flux was a rosin-based mildly activated (RMA) solution. The Ni-Pd-Au finish was tested in the as-fabricated condition as well as after exposure to one of the following accelerated storage (shelf life) regiments: (1) 33.6, 67.2, or 336 hours in the Battelle Class 2 flowing gas environment or (2) 5, 16, or 24 hours of steam aging (88ºC, 90%RH).
Technical Library | 2019-01-09 19:19:52.0
The electronics industry has widely adopted Sn-3.0Ag-0.5Cu solder alloys for lead-free reflow soldering applications and tin-copper based alloys for wave soldering applications. In automated soldering or rework operations, users may work with Sn-Ag-Cu or Sn-Cu based alloys. One of the challenges with these types of lead-free alloys for automated / hand soldering operations, is that the life of the soldering iron tips will shorten drastically using lead-free solders with an increased cost of soldering iron tool maintenance/ tip replacement. Development was done on a new lead-free low silver solder rework alloy (Sn-0.3Ag-0.7Cu-0.04Co) in comparison with a number of alternative lead-free alloys including Sn-0.3Ag-0.7Cu, Sn-0.7Cu and Sn-3.0Ag-0.5Cu and tin-lead Sn40Pb solder in soldering evaluations.
Technical Library | 2015-01-28 17:39:34.0
Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology.
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