Technical Library | 1999-05-06 15:31:13.0
Tin plating on a component lead makes its soldering easier. Everybody knows that. Not so well known is that tin plating has shelf life -- its ability to be easily soldered degrades over time. the speed and severity of degradation depends both on storage conditions and on the plating itself...
Technical Library | 2022-10-31 17:30:40.0
This paper presents a quantitative analysis of solder joint reliability data for lead-free Sn-Ag-Cu (SAC) and mixed assembly (SnPb + SAC) circuit boards based on an extensive, but non-exhaustive, collection of thermal cycling test results. The assembled database covers life test results under multiple test conditions and for a variety of components: conventional SMT (LCCCs, resistors), Ball Grid Arrays, Chip Scale Packages (CSPs), wafer-level CSPs, and flip-chip assemblies with and without underfill. First-order life correlations are developed for SAC assemblies under thermal cycling conditions. The results of this analysis are put in perspective with the correlation of life test results for SnPb control assemblies. Fatigue life correlations show different slopes for SAC versus SnPb assemblies, suggesting opposite reliability trends under low or high stress conditions. The paper also presents an analysis of the effect of Pb contamination and board finish on lead-free solder joint reliability. Last, test data are presented to compare the life of mixed solder assemblies to that of standard SnPb assemblies for a wide variety of area-array components. The trend analysis compares the life of area-array assemblies with: 1) SAC balls and SAC or SnPb paste; 2) SnPb balls assembled with SAC or SnPb paste.
Technical Library | 2024-06-19 13:59:50.0
The solderability of a nickel-palladium-gold (Ni-Pd-Au) finish on a Cu substrate was evaluated for the Pb-free solder, 95.5Sn-3.9Ag-0.6 Cu (wt.%, abbreviated Sn-Ag-Cu) and the eutectic 63Sn-37 Pb (Sn-Pb) alloy. The solder temperature was 245ºC. The flux was a rosin-based mildly activated (RMA) solution. The Ni-Pd-Au finish was tested in the as-fabricated condition as well as after exposure to one of the following accelerated storage (shelf life) regiments:
Technical Library | 2020-10-27 02:02:17.0
Solder powder size is a popular topic in the electronics industry due to the continuing trend of miniaturization of electronics. The question commonly asked is "when should we switch from Type 3 to a smaller solder powder?" Solder powder size is usually chosen based on the printing requirements for the solder paste. It is common practice to use IPC Type 4 or 5 solder powders for stencil designs that include area ratios below the recommended IPC limit of 0.66. The effects of solder powder size on printability of solder paste have been well documented. The size of the solder powder affects the performance of the solder paste in other ways. Shelf life, stencil life, reflow performance, voiding behavior, and reactivity / stability are all affected by solder powder size. Testing was conducted to measure each of these solder paste performance attributes for IPC Type 3, Type 4, Type 5 and Type 6 SAC305 solder powders in both water soluble and no clean solder pastes. The performance data for each size of solder powder in each solder paste flux was quantified and summarized. Guidance for choosing the optimal size of solder powder is given based on the results of this study.
Technical Library | 2022-03-02 21:26:51.0
The solderability of a nickel-palladium-gold (Ni-Pd-Au) finish on a Cu substrate was evaluated for the Pb-free solder, 95.5Sn-3.9Ag-0.6 Cu (wt.%, abbreviated Sn-Ag-Cu) and the eutectic 63Sn-37 Pb (Sn-Pb) alloy. The solder temperature was 245ºC. The flux was a rosin-based mildly activated (RMA) solution. The Ni-Pd-Au finish was tested in the as-fabricated condition as well as after exposure to one of the following accelerated storage (shelf life) regiments: (1) 33.6, 67.2, or 336 hours in the Battelle Class 2 flowing gas environment or (2) 5, 16, or 24 hours of steam aging (88ºC, 90%RH).
Technical Library | 2024-06-19 15:23:54.0
Each year the semiconductor industry routes a significant volume of devices to recycling sites for no reliability or quality rationale beyond the fact that those devices were stored on a warehouse shelf for two years. This study identifies the key risks attributed to extended storage of devices in uncontrolled indoor environments and the risk mitigation required to permit safe shelf-life extension. Component reliability was evaluated after extended storage to assure component solderability, MSL stability and die surface integrity. Packing materials were evaluated for customer use parameters as well as structural integrity and ESD properties. Results show that current packaging material (mold compound and leadframe) is sufficiently robust to protect the active integrated circuits for many decades and permit standard reflow solder assembly beyond 15 years. Standard packing materials (bags, desiccant, and humidity cards) are robust for a 32 month storage period that can be extended by repacking with fresh materials. Packing materials designed for long term storage are effective for more than five years.
Technical Library | 2021-01-28 01:55:00.0
Printed circuit board surface finishes are a topic of constant discussion as environmental influences, such as the Restriction of Hazardous Substances (RoHS) Directive or technology challenges, such as flip chip and 01005 passive components, initiate technology changes. These factors drive the need for greater control of processing characteristics like coplanarity and solderability, which influence the selection of surface finishes and impact costs as well as process robustness and integrity. The ideal printed circuit board finish would have good solderability, long shelf life, ease of fabrication/processing, robust environmental performance and provide dual soldering/wirebonding capabilities; unfortunately no single industry surface finish possesses all of these traits. The selection of a printed circuit board surface finish is ultimately a series of compromises for a given application.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2016-01-21 16:52:27.0
Solder paste has long been viewed as "black magic". This "black magic" can easily be dispelled through a solder paste evaluation. Unfortunately, solder paste evaluation can be a challenge for electronic assemblers. Interrupting the production schedule to perform an evaluation is usually the first hurdle. Choosing the solder paste properties to test is simple, but testing for these properties can be difficult. Special equipment or materials may be required depending upon the tests that are chosen. Once the testing is complete, how does one make the decision to choose a solder paste? Is the decision based on gut feel or hard data?This paper presents a process for evaluating solder pastes using a variety of methods. These methods are quick to run and are challenging, revealing the strengths and weaknesses of solder pastes. Methods detailed in this paper include: print volume, stencil life, response to pause, open time, tack force over time, wetting, solder balling, graping, voiding, accelerated aging, and others.
| 1 |
