Technical Library | 2009-12-09 19:28:28.0
A fundamental evaluation of a variety of approaches for designing a high-speed (10 Gb/s) serial differential electrical channel is examined. The application of the electrical interface has been simulated using HSpice software. It demonstrated how the signal quality could be affected by the use of microstrip versus stripline traces and their associated advantages and disadvantages is discussed. Example XFI channels were assembled from the simulation results to demonstrate viability of the application.
Technical Library | 2021-09-15 18:58:01.0
Mathematical model for dynamic force analysis of printed circuit boards has been designed to calculate dynamic deformations and stresses in printed circuit boards and assess their dynamic strength and rigidity. The represented model describes a printed circuit board as a separate oscillatory system, which is simulated as prismatic beam set on two oscillating supports. Simulation and assessment of stress and deflection in printed circuit boards and obtaining their amplitude frequency responses provided recommendations, which ensure strength and stiffness of printed circuit boards subjected to dynamic loads..
Technical Library | 2021-06-15 18:40:53.0
The jet printing of a dense mixed non-Newtonian suspension is based on the rapid displacement of fluid through a nozzle, the forming of a droplet and eventually the break-off of the filament. The ability to model this process would facilitate the development of future jetting devices. The purpose of this study is to propose a novel simulation framework and to show that it captures the main effects such as droplet shape, volume and speed. In the framework, the time dependent flow and the fluid-structure interaction between the suspension, the moving piston and the deflection of the jetting head is simulated. The system is modelled as a two phase system with the surrounding air being one phase and the dense suspension the other. Hence, the non-Newtonian suspension is modelled as a mixed single phase with properties determined from material testing. The simulations were performed with two coupled in-house solvers developed at Fraunhofer-Chalmers Centre; IBOFlow, a multiphase flow solver and LaStFEM, a large strain FEM solver. Jetting behaviour was shown to be affected not only by piston motion and fluid rheology, but also by the energy loss in the jetting head. The simulation results were compared to experimental data obtained from an industrial jetting head.
Fraunhofer-Chalmers Research Centre for Industustrial Mathematics
Technical Library | 2012-02-16 16:53:16.0
Channel simulations are only as accurate as the models used to develop them. While we have seen much effort placed on printed circuit board (PCB) materials (copper finish, dielectric moisture absorption), other elements within the channel have been largel
Technical Library | 2020-12-24 02:50:56.0
A method for packaging integrated circuit silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm×8 mm× 0.53 mm and 2 mm×2 mm×0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three underfill adhesives (EP30AO, EP37-3FLF, and Epo-Tek 301 2fl), three highly flexible adhesives (Loctite 4860, Loctite 480, and Loctite 4902), and three substrates (Kapton,Mylar, and PEEK) have been evaluated, and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, was identified as the best materials combination with the optimum underfill and substrate thickness identified as 0.05 mm.
Technical Library | 2021-12-21 23:11:50.0
This paper cover the following points: - Objective 01: Preprocessing, - Introduction, - Objective 02: Automated FE Scripting, - Objective 03: Postprocessing, Reliability Analysis of PTHs, - Objective 03: Postprocessing, Manufacturability of Microvias
Technical Library | 2014-04-03 18:01:13.0
A system level modeling methodology is presented and validated on a simple case. It allows precise simulations of electrostatic discharge (ESD) stress propagation on a printed circuit board (PCB). The proposed model includes the integrated circuit (IC) ESD protection network, IC package, PCB lines, passives components, and externals elements. The impact of an external component on the ESD propagation paths into an IC is demonstrated. Resulting current and voltage waveforms are analyzed to highlight the interactions between all the elements of an operating PCB. A precise measurement technique was designed and used to compare with the simulation results. The model proposed in this paper is able to predict, with good accuracy, the propagation of currents and voltages into the whole system during ESD stress. It might be used to understand why failures occur and how to fix them with the most suitable solution.
Technical Library | 2016-06-23 13:24:56.0
Proper assembly of components is critical in the manufacturing industry as it affects functionality and reliability. In a heat sink assembly, a detailed manual process is often utilized. However, an automated fixture is used whenever applicable.This paper will illustrate the use of strain gauge testing and Finite Element Analysis (FEA) as a simulation tool to evaluate and optimize the heat sink assembly process by manual and automated methods. Several PCBAs in the production line were subjected to the manual and automated assembly process. Strain gauge testing was performed and FEA models were built and run. Results were compared with the goal of improving the FEA model. The updated FEA model will be used in simulating different conditions in assembly. Proposed improvement solutions to some issues can also be verified through FEA.
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
Technical Library | 2023-03-13 19:35:47.0
Translational Research in Additive Manufacturing at GTMI * Additive manufacturing/3D printing process and equipment development (e.g., metal, polymer and composites part manufacturing) * Computational modeling and simulation of additive manufacturing/printed electronics processes * Advanced materials development for additive manufacturing/printed electronics * Application development and demonstration of additive manufacturing/printed electronics
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