Technical Library | 2009-11-05 11:17:32.0
Head-in-pillow (HiP), also known as ball-and-socket, is a solder joint defect where the solder paste deposit wets the pad, but does not fully wet the ball. This results in a solder joint with enough of a connection to have electrical integrity, but lacking sufficient mechanical strength. Due to the lack of solder joint strength, these components may fail with very little mechanical or thermal stress. This potentially costly defect is not usually detected in functional testing, and only shows up as a failure in the field after the assembly has been exposed to some physical or thermal stress.
Technical Library | 2009-01-15 00:42:58.0
Tin-silver-copper has received much publicity in recent years as the lead-free solder of choice. SAC305 was endorsed by the IPC Solder Value Product Council in the United States as the preferred option for SMT assembly; most assemblers have transitioned to this alloy for their solder paste requirements. The SAC305 alloy due to its 3.0% content of silver is expensive when compared to traditional 63/37 for this reason many wave assemblers are opting for less costly options such as tin-copper based solders for their wave, selective and dip tinning operations.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2016-01-12 11:05:28.0
The electronic industry is currently very interested in low temperature soldering processes such as using Sn/Bi alloy to improve process yield, eliminate the head-in-pillow effect, and enhance rework yield. However, Sn/Bi alloy is not strong enough to replace lead-free (SAC) and eutectic Sn/Pb alloys in most applications. In order to improve the strength of Sn/Bi solder joints, enhance mechanical performance, and improve reliability properties such as thermal cycling performance of soldered electronic devices, YINCAE has developed a low temperature solder joint encapsulant for Sn/Bi soldering applications. This low temperature solder joint encapsulant can be dipped, dispensed, or printed. After reflow with Sn/Bi solder paste or alloy, solder joint encapsulant encapsulates the solder joint. As a result, the strength of solder joints is enhanced by several times, and thermal cycling performance is significantly improved. All details will be discussed in this paper.
Technical Library | 2018-08-29 21:17:53.0
No-clean solder pastes are widely used in a number of applications that are exposed to wide variations in temperature during the life of the assembled electronics device. Some have observed that cracks can and do form in flux residue and have postulated that this is the result of or exacerbated by temperature cycling. Furthermore, the potential exists for the flux residue to soften or liquefy at elevated temperatures, and even flow if orientated parallel to gravity. In situations such as in automotive electronics, where significant temperature cycling is a reality and high reliability is a must, concern sometimes exists that the cracking and possible softening or liquefying of the residue may have a deleterious effect on the electrical reliability of the flux residue. This paper will attempt to address this concern.
Technical Library | 2018-02-28 22:28:30.0
Circuit functional density requirements continue to drive innovative approaches to high performance packaging. Some new approaches include; aggressive space reduction, embedded solutions, and those that offer some form of risk reduction and rework potential are now options that are being explored by customers. Requirements for assembly of these types of packages necessitate the deposition of solder paste and assembly of components into cavities of the substrates to gain z-axis density as well as area functional density. Advances in the fabrication of PWB’s with cavities using newly developed laser micro-fabrication processes along with increased circuit pitch density of 50 micron lines and spaces permit new applications for high performance electronic substrates. First published at SMTA Pan Pacific Symposium
Technical Library | 2013-02-08 22:56:47.0
Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.
Technical Library | 2023-05-02 18:50:24.0
Surface-mount PCB components are smaller than their lead-based counterparts and provide a radically higher component density. They are available in a variety of shapes and sizes designated by a series of standardized codes curated by the electronics industry. Of these PCB components, the 0201-sized are the smallest, measuring 0.024 x 0.012 in. (0.6 x 0.3 mm) – that's 70% smaller than the previous 0402 level! The 0201 components are designed to improve reliability in space-constrained applications such as portable electronics like smartphones, tablets, robotics and digital cameras, but require delicate handling during the assembly process. Given the miniaturized dimensions of an 0201 package, it is crucial that the mounting process abide by a series of guidelines regarding the design of the PCB mounting pads and solderable metallization, PCB circuit trace width, solder paste selection, package placement and overages, solder paste reflow, solder stencil screening, and final inspection. It's advisable that one review this information when procuring the services of a PCB assembler.
Technical Library | 2001-05-03 11:23:09.0
In this age of global competition, world class electronics manufacturers understand that increasing profit margins is accomplished not by increasing price or lowering the quality of components and workmanship, but by increasing production yields. Post-solder inspection ensures that your customers receive good product, but by separating the good boards from the bad boards you only measure yield, not improve it. A yield (and profit) improvement strategy consists of making measurements at critical stages, as early as possible in the assembly process, and adjusting the process parameters to achieve optimal performance.
Technical Library | 2013-06-05 23:14:44.0
The combination of higher lead-free process temperatures, smaller print deposits, and temperature restraints on electrical components has created difficult challenges in optimizing the reflow process. Not only are the electronic components and the PWB at risk, but the ability to achieve a robust solder joint becomes difficult, especially if the PCB is thermally massive. In addition, the constant miniaturization of electronic components, hence smaller solder paste deposits, may require the use of smaller particle-sized powders (...) This paper is a summary of best practices in optimizing the reflow process to meet these challenges of higher reflow temperatures, smaller print deposits, decreased powder particle size, and their affect on the reflow process.
