Technical Library | 2015-04-02 20:12:58.0
The demands on volume delivery and positioning accuracy for solder paste deposits are increasing as the size and complexity of circuits continue to develop in the electronics industry. According to the iNEMI 2013 placement accuracy for these kinds of components will reach 6 sigma placement accuracy in X and Y of 30 um by 2023.This study attempts to understand the dependencies on piezo actuation pulse profile on jetting deposit quality, especially focused on positioning, satellites and shape. The correlation of deposit diameter and positioning deviation as a function of piezo actuation profile shows that positioning error for deposits increase almost monotonically with decreasing droplet volume irrespective of the piezo-actuation profile. The trends for shape and satellite levels are not as clear and demand further study.
Technical Library | 2019-04-07 22:47:46.0
How to protect your PCB from moisture related damage? J-STD-033 put forward stricter regulation on the MSD exposure environment,when the exposure time exceed the tolerated,the moisture will penetrate into electronics,Moreover, the newest RoHS regulation will rise soldering temperature,the sudden high temperature will lead to expansion and cracking on electronic components. In order to decrease the moisture defect on PCB for the manufacturers in China,Climatest Symor® begin to concentrated on electronic dry cabinet R&D since early 1990s,we specialize in handling temperature and humidity for 20 years,and we provide best solution for PCB storage.
Technical Library | 2015-12-31 15:19:28.0
Today's consumer electronic product are characterized by miniatuization, portability and light weight with high performance, especially for 3G mobile products. In the future more fine pitch CSPs (0.4mm) component will be required. However, the product reliability has been a big challenge with the fine pitch CSP. Firstly, the fine pitch CSPs are with smaller solder balls of 0.25mm diameter or even smaller. The small solder ball and pad size do weaken the solder connection and the adhesion of the pad and substrate, thus the pad will peel off easily from the PCB substrate. In addition, miniature solder joint reduce the strength during mechanical vibration, thermal shock, fatigue failure, etc. Secondly, applying sufficient solder paste evenly on the small pad of the CSP is difficult because stencil opening is only 0.25mm or less. This issue can be solved using the high end type of stencil such as Electroforming which will increase the cost.
Technical Library | 2015-07-01 16:51:43.0
Aerospace and military companies continue to exercise RoHS exemptions and to intensively research the long term attachment reliability of RoHS compliant solders. Their products require higher vibration, drop/shock performance, and combined-environment reliability than the conventional SAC305 alloy provides. The NASA-DoD Lead-Free Electronics Project confirmed that pad cratering is one of the dominant failure modes that occur in various board level reliability tests, especially under dynamic loading. One possible route to improvement of the mechanical and thermo-mechanical properties of solder joints is the use of Pb-free solders with lower process temperatures. Lower temperatures help reduce the possibility of damaging the boards and components, and also may allow for the use of lower Tg board materials which are less prone to pad cratering defects. There are several Sn-Ag-Bi and Sn-Ag-Cu-Bi alloys which melt about 10°C lower than SAC305. The bismuth in these solder compositions not only reduces the melting temperature, but also improves thermo-mechanical behavior. An additional benefit of using Bi-containing solder alloys is the possibility to reduce the propensity to whisker growth
Technical Library | 2017-10-12 15:45:25.0
The risk associated with whisker growth from pure tin solderable terminations is fully mitigated when all of the pure tin is dissolved into tin-lead solder during SMT reflow. In order to take full advantage of this phenomenon, it is necessary to understand the conditions under which such coverage can be assured. A round robin study has been performed by IPC Task group 8-81f, during which identical sets of test vehicles were assembled at multiple locations, in accordance with IPC J-STD-001, Class 3. All of the test vehicles were analyzed to determine the extent of complete tin dissolution on a variety of component types. Results of this study are presented together with relevant conclusions and recommendations to guide high reliability end-users on the applicability and limitations of this mitigation strategy.
Technical Library | 2023-11-06 17:08:44.0
A new process has been developed for RF shielding on compact electronic communications devices using automated solder paste dispensing. The process is known as Shield Edge Interconnect (SEI). SEI designs enable parts to be processed though underfill before placing of the RF shield and allows more complete use of valuable PCB real estate to achieve reduced form factor requirements and/or for added components on products such as smartphones and tablets. The reduced form factor creates challenges for the assembly of those devices. This process, enabled by Speedline dispensing technology, relies on extremely accurate dispensing of solder paste on copper traces located along the outer edge of the PCB. The result is a robust process solution for SEI in which proprietary closed loop dispenser, pump, vision, and software technologies enable a high volume manufacturing (HVM) process.
Technical Library | 2023-07-25 16:50:02.0
Some of the new handheld communication devices offer real challenges to the paste printing process. Normally, there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils. This paper will explore a different type of step stencil for this application; a "Two-Print Stencil Process" step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005, 0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil. Design guidelines for minimum keep-out distances between the relief step, the fine pitch apertures, and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.
Technical Library | 2018-02-28 22:28:30.0
Circuit functional density requirements continue to drive innovative approaches to high performance packaging. Some new approaches include; aggressive space reduction, embedded solutions, and those that offer some form of risk reduction and rework potential are now options that are being explored by customers. Requirements for assembly of these types of packages necessitate the deposition of solder paste and assembly of components into cavities of the substrates to gain z-axis density as well as area functional density. Advances in the fabrication of PWB’s with cavities using newly developed laser micro-fabrication processes along with increased circuit pitch density of 50 micron lines and spaces permit new applications for high performance electronic substrates. First published at SMTA Pan Pacific Symposium
Technical Library | 2023-05-02 19:06:43.0
As 0402 has become a common package for printed circuit board (PCB) assembly, research and development on mounting 0201 components is emerging as an important topic in the field of surface mount technology for PWB miniaturization. In this study, a test vehicle for 0201 packages was designed to investigate board design and assembly issues. Design of Experiment (DOE) was utilized, using the test vehicle, to explore the influence of key parameters in pad design, printing, pick-andplace, and reflow on the assembly process. These key parameters include printing parameters, mounting height or placement pressure, reflow ramping rate, soak time and peak temperature. The pad designs consist of rectangular pad shape, round pad shape and home-based pad shape. For each pad design, several different aperture openings on the stencil were included. The performance parameters from this experiment include solder paste height, solder paste volume and the number of post-reflow defects. By analyzing the DOE results, optimized pad designs and assembly process parameters were determined.
Technical Library | 2018-09-26 20:33:26.0
Bottom terminated components, or BTCs, have been rapidly incorporated into PCB designs because of their low cost, small footprint and overall reliability. The combination of leadless terminations with underside ground/thermal pads have presented a multitude of challenges to PCB assemblers, including tilting, poor solder fillet formation, difficult inspection and – most notably – center pad voiding. Voids in large SMT solder joints can be difficult to predict and control due to the variety of input variables that can influence their formation. Solder paste chemistries, PCB final finishes, and reflow profiles and atmospheres have all been scrutinized, and their effects well documented. Additionally, many of the published center pad voiding studies have focused on optimizing center pad footprint and stencil aperture designs. This study focuses on I/O pad stencil modifications rather than center pad modifications. It shows a no-cost, easily implemented I/O design guideline that can be deployed to consistently and repeatedly reduce void formation on BTC-style packages.
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