Technical Library | 2017-02-23 17:23:16.0
Managing the environmental performance of products is an increasingly complicated challenge for manufacturers today. These companies face a complex tangle of requirements and mandates from regulators, consumers and customers to manage the toxicity, recycleability and overall environmental impact of their products. Not only have governments, business-to-business customers and consumers demonstrated a clear preference for better environmentally performing and "greener" brands, but investors are now pressuring manufacturers, as well. For example, the Dow Jones Sustainability Index identifies and tracks leading sustainability-driven companies around the world. This paper focuses on the challenges companies face and the best practices they can employ when collecting substance, material and compliance data from their suppliers and supply chain.
Technical Library | 2024-04-22 20:16:01.0
The solid-state electronics industry faces relentless pressure to improve performance, increase functionality, decrease costs, and reduce design and development time. As a result, device feature sizes are now in the nanometer scale range and design life cycles have decreased to fewer than five years. Until recently, semiconductor device lifetimes could be measured in decades, which was essentially infinite with respect to their required service lives. It was, therefore, not critical to quantify the device lifetimes exactly, or even to understand them completely. For avionics, medical, military, and even telecommunications applications, it was reasonable to assume that all devices would have constant and relatively low failure rates throughout the life of the system; this assumption was built into the design, as well as reliability and safety analysis processes.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
Technical Library | 2023-05-02 19:06:43.0
As 0402 has become a common package for printed circuit board (PCB) assembly, research and development on mounting 0201 components is emerging as an important topic in the field of surface mount technology for PWB miniaturization. In this study, a test vehicle for 0201 packages was designed to investigate board design and assembly issues. Design of Experiment (DOE) was utilized, using the test vehicle, to explore the influence of key parameters in pad design, printing, pick-andplace, and reflow on the assembly process. These key parameters include printing parameters, mounting height or placement pressure, reflow ramping rate, soak time and peak temperature. The pad designs consist of rectangular pad shape, round pad shape and home-based pad shape. For each pad design, several different aperture openings on the stencil were included. The performance parameters from this experiment include solder paste height, solder paste volume and the number of post-reflow defects. By analyzing the DOE results, optimized pad designs and assembly process parameters were determined.
