Technical Library | 2011-01-20 18:43:39.0
PCB stack-up is an important factor in determining the EMC performance of a product. A good stack-up can be very effective in reducing radiation from the loops on the PCB (differential-mode emission), as well as the cables attached to the board (common-mo
Technical Library | 2015-05-14 15:45:45.0
The Printed Circuit Board industry has seen a steady reduction in pitch from 1.0mm to 0.4mm; a segment of the industry is even using or considering a 0.25mm pitch. This has increased the use of stacked microvias in these designs. The process of stacking microvias has been practiced for several years in handheld devices; however, the devices generally do not operate in harsh conditions. Type 1 and Type 2 microvias have been tested over the years and have been found to be very reliable. We do not have enough test data for 3 and 4 stack microvias when placed on and off buried via. The main objective of this study was to understand the reliability of 3 and 4 stack microvias placed on and off a buried via.
Technical Library | 2018-12-12 22:20:22.0
Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard, readily available device packaging methods in which high-density packaging is achieved by: (1) using standard "packaged" memory devices, (2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads, stacked either 2-high or 4-high, and integrated into a single dual-flat-no-lead (DFN) package.
Technical Library | 2010-12-02 20:09:41.0
Planning the multilayer PCB stackup configuration is one of the most important aspects in achieving the best possible performance of a product. A correctly stacked PCB substrate ca effectively reduce electromagnetic emissions, crosstalk and also make the
Technical Library | 2012-03-22 20:40:01.0
Miniaturization continues to be a driving force in both integrated circuit packaging and printed circuit board laminate technology. In addition to decreasing component pitch (lead to lead spacing), utilization of the vertical space by stacking packages ha
Technical Library | 2009-04-30 18:06:24.0
This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.
Technical Library | 2014-02-27 15:30:20.0
Silicon dioxide is normally used as filler in underfill. The thermal conductivity of underfill is less than 1 w/mk, which is not able to meet the current flip chip application requirements such as 3D stacked multi-chips packaging. No matter which direction the heat will be dissipated through PCB or chip, the heat has to pass through the underfill in 3D stacked chips. Therefore the increase of thermal conductivity of underfill can significantly enhance the reliability of electronic devices, particularly in 3D package devices
Technical Library | 2017-12-27 22:52:43.0
To compensate for the insufficiency and instability of solder paste dispensing and printing that are used in the SMT production process, a noncontact solder paste jetting system driven by a piezoelectric stack based on the principle of the nozzle-needle-system is introduced in this paper, in which a miniscule gap exists between the nozzle and needle during the jetting process.
Technical Library | 2012-09-20 21:45:38.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. An evaluation of four FR4 laminates in commonly used stack-ups was done to determine their survivability for the Pb-free HASL process followed by a worst case Pb-free manufacturin
Technical Library | 2021-12-21 23:21:34.0
Points of discussion in "HDI Microvia Technology – Cost Aspects" are: - Reasons for the use of HDI technology - Printed circuit board (PCB) size - Number of layers - Stack-up and complexity - Other important cost influences -–Design rules -–Drilling costs -–Microvia filling
