Technical Library | 2017-08-17 12:28:30.0
At SMT assembly, flux outgassing/drying is difficult for devices with poor venting channel, and resulted in insufficiently dried/burnt-off flux residue for no-clean process. Examples including: Large low stand-off components such as QFN, LGA Components covered under electromagnetic shield which has either no or few venting holes Components assembled within cavity of board Any other devices with small open space around solder joints
Technical Library | 2019-07-23 22:33:47.0
The Quad Flat Pack No Leads (QFN) style of leadless packaging [also known as a Land Grid Array (LGA)] is rapidly increasing in us e for wireless, automotive, telecom and many other areas becaus e of its low cost, low stand-off height and excellent thermal and electri cal properties. With the implementation of any new package type, there is always a learning curve for its use in design and processing as well as for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. Therefore, this paper will provide examples of the common process defects that can be seen with QFNs /LGAs when using optical and x-ray inspection as part of manufacturing quality control. Results of trials conducted on four PCB finishes and using vapour phase and convection reflow will be discussed.
Technical Library | 2016-12-29 15:37:51.0
The reliabilities of the flux residue of electronic assemblies and semiconductor packages are attracting more and more attention with the adoption of no-clean fluxes by majority of the industry. In recent years, the concern of "partially activated" flux residue and their influence on reliability have been significantly raised due to the miniaturization along with high density design trend, selective soldering process adoption, and the expanded use of pallets in wave soldering process. When flux residue becomes trapped under low stand-off devices, pallets or unsoldered areas (e.g. selective process), it may contain unevaporated solvent, "live" activators and metal complex intermediates with different chemical composition and concentration levels depending on the thermal profiles. These partially-activated residues can directly impact the corrosion, surface insulation and electrochemical migration of the final assembly. In this study, a few application tests were developed internally to understand this issue. Two traditional liquid flux and two newly developed fluxes were selected to build up the basic models. The preliminary results also provide a scientific approach to design highly reliable products with the goal to minimize the reliability risk for the complex PCB designs and assembly processes. This paper was originally published by SMTA in the Proceedings of SMTA International
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
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