Technical Library | 2014-02-20 15:59:17.0
In this chapter, we discuss the type of parts used to create counterfeits and the defects/degradations inherent in these parts due to the nature of the sources they come from, proposed inspection standards, and limitations of these standards. The processes used to modify the packaging of these parts to create counterfeits are then discussed along with the traces left behind from each of the processes. We then present a systematic methodology for detecting signs of possible part modifications to determine the risk of a part or part lot being counterfeit.
Technical Library | 2018-01-04 11:05:34.0
Traceability has grown from being a specialized need for certain safety critical segments of the industry, to now being a recognized value-add tool for the industry as a whole. The perception of traceability data collection however persists as being a burden that may provide value only when the most rare and disastrous of events take place. Disparate standards have evolved in the industry, mainly dictated by large OEM companies in the market create confusion, as a multitude of requirements and definitions proliferate. The intent of the IPC-1782 project is to bring the whole principle and perception of traceability up to date. Traceability, as defined in this standard will represent the most effective quality tool available, becoming an intrinsic part of best practice operations, with the encouragement of automated data collection from existing manufacturing systems, integrating quality, reliability, predictive (routine, preventative, and corrective) maintenance, throughput, manufacturing, engineering and supply-chain data, reducing cost of ownership as well as ensuring timeliness and accuracy all the way from a finished product back through to the initial materials and granular attributes about the processes along the way.
Technical Library | 2015-06-04 19:10:47.0
Integrators and designers of high-reliability systems exert little or no control over component-level plating processes that affect the propensity for tin whiskering. Challenges of how to assure long-term reliability, while continuing to use COTS parts plated with pure tin, continue to arise. An integrated, quantitative, standardized methodology is proposed whereby mitigation levels can be selected that are appropriate for specific applications of pure tin for given end-uses. A system of hardware end-use classification is proposed, together with recommended appropriate risk mitigation approaches. An updated version of the application-specific risk assessment algorithm is presented together with recommended thresholds for acceptability within the context of the hardware classifications.
Technical Library | 2021-02-17 22:13:39.0
The development of various biosensors has revolutionized the healthcare industry by providing rapid and reliable detection capability. Printed circuit board (PCB) technology has a well-established industry widely available around the world. In addition to electronics, this technology has been utilized to fabricate electrical parts, including electrodes for different biological and chemical sensors. High reproducibility achieved through long-lasting standard processes and low-cost resulting from an abundance of competitive manufacturing services makes this fabrication method a prime candidate for patterning electrodes and electrical parts of biosensors. The adoption of this approach in the fabrication of sensing platforms facilitates the integration of electronics and microfluidics with biosensors. In this review paper, the underlying principles and advances of printed board circuit technology are discussed. In addition, an overview of recent advancements in the development of PCB-based biosensors is provided. Finally, the challenges and outlook of PCB-based sensors are elaborated. doi:10.3390/bios10110159
Technical Library | 2024-04-29 21:39:52.0
In this paper, we develop and put into practice an Automatic Optical Inspection (AOI) system based on machine vision to check the holes on a printed circuit board (PCB). We incorporate the hardware and software. For the hardware part, we combine a PC, the three-axis positioning system, a lighting device and CCD cameras. For the software part, we utilize image registration, image segmentation, drill numbering, drill contrast, and defect displays to achieve this system. Results indicated that an accuracy of 5µm could be achieved in errors of the PCB holes allowing comparisons to be made. This is significant in inspecting the missing, the multi-hole and the incorrect location of the holes. However, previous work only focusses on one or other feature of the holes. Our research is able to assess multiple features: missing holes, incorrectly located holes and excessive holes. Equally, our results could be displayed as a bar chart and target plot. This has not been achieved before. These displays help users analyze the causes of errors and immediately correct the problems. Additionally, this AOI system is valuable for checking a large number of holes and finding out the defective ones on a PCB. Meanwhile, we apply a 0.1mm image resolution which is better than others used in industry. We set a detecting standard based on 2mm diameter of circles to diagnose the quality of the holes within 10 seconds.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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