Technical Library | 2016-06-16 15:29:31.0
Embedding components within the PC board structure is not a new concept. Until recently, however, most embedded component PC board applications adapted only passive elements. The early component forming processes relied on resistive inks and films to enable embedding of resistor and capacitors elements. Although these forming methods remain viable, many companies are choosing to place very thin discrete passive components and semiconductor die elements within the PC board layering structure. In addition to improving the products performance, companies have found that by reducing the component population on the PC board's surface, board level assembly is less complex and the PC board can be made smaller, The smaller substrate, even when more complex, often results in lower cost. Although size and cost reductions are significant attributes, the closer coupling of key elements can also contribute to improving functional performance.This paper focuses on six basic embedded component structure designs described in IPC-7092.
Technical Library | 2020-09-08 16:43:32.0
Atomic layer deposition (ALD) is an ultra-thin film deposition technique that has found many applications owing to its distinct abilities. They include uniform deposition of conformal films with controllable thickness, even on complex three-dimensional surfaces, and can improve the efficiency of electronic devices. This technology has attracted significant interest both for fundamental understanding how the new functional materials can be synthesized by ALD and for numerous practical applications, particularly in advanced nanopatterning for microelectronics, energy storage systems, desalinations, catalysis and medical fields. This review introduces the progress made in ALD, both for computational and experimental methodologies, and provides an outlook of this emerging technology in comparison with other film deposition methods. It discusses experimental approaches and factors that affect the deposition and presents simulation methods, such as molecular dynamics and computational fluid dynamics, which help determine and predict effective ways to optimize ALD processes, hence enabling the reduction in cost, energy waste and adverse environmental impacts. Specific examples are chosen to illustrate the progress in ALD processes and applications that showed a considerable impact on other technologies.
Technical Library | 2023-03-16 18:51:43.0
Conductive anodic filament (CAF) formation was first reported in 1976.1 This electrochemical failure mode of electronic substrates involves the growth of a copper containing filament subsurface along the epoxy-glass interface, from anode to cathode. Despite the projected lifetime reduction due to CAF, field failures were not identified in the 1980s. Recently, however, field failures of critical equipment have been reported.2 A thorough understanding of the nature of CAF is needed in order to prevent this catastrophic failure from affecting electronic assemblies in the future. Such an understanding requires a comprehensive evaluation of the factors that enhance CAF formation. These factors can be grouped into two types: (1) internal variables and (2) external influences. Internal variables include the composition of the circuit board material, and the conductor metallization and configuration (i.e. via to via, via to surface conductor or surface conductors to surface conductors). External influences can be due to (1) production and (2) storage and use. During production, the flux or hot air solder leveling (HASL) fluid choice, number and severity of temperature cycles, and the method of cleaning may influence CAF resistance. During storage and use, the principal concern is moisture uptake resulting from the ambient humidity. This paper will report on the relationship between these various factors and the formation of CAF. Specifically, we will explore the influences of printed wiring board (PWB) substrate choice as well as the influence of the soldering flux and HASL fluid choices. Due to the ever-increasing circuit density of electronic assemblies, CAF field failures are expected to increase unless careful attention is focused on material and processing choices.
Technical Library | 2013-01-17 15:37:21.0
A problem exists with electroless nickel / immersion gold (ENIG) surface finish on some pads, on some boards, that causes the solder joint to separate from the nickel surface, causing an open. The solder has wet and dissolved the gold. A weak tin to nickel intermetallic bond initially occurs, but the intermetallic bond cracks and separates when put under stress. Since the electroless nickel / immersion gold finish performs satisfactory in most applications, there had to be some area within the current chemistry process window that was satisfactory. The problem has been described as a 'BGA Black Pad Problem' or by HP as an 'Interfacial Fracture of BGA Packages…'[1]. A 24 variable experiment using three different chemistries was conducted during the ITRI (Interconnect Technology Research Institute) ENIG Project, Round 1, to investigate what process parameters of the chemical matrix were potentially satisfactory to use and which process parameters of the chemical matrix need to be avoided. The ITRI ENIG Project has completed Round 1 of testing and is now in the process of Round 2 TV (Test Vehicle) build.
Technical Library | 2021-11-17 18:53:50.0
The demand for product miniaturization, especially in the handheld device area, continues to challenge the board assembly industry. The desire to incorporate more functionality while making the product smaller continues to push board design to its limit. It is not uncommon to find boards with castle-like components right next to miniature components. This type of board poses a special challenge to the board assemblers as it requires a wide range of paste volume to satisfy both small and large components. One way to address the printing challenge is to use creative stencil design to meet the solder paste requirement for both large and small components. ... The most important attribute of a stencil is its release characteristic. In other words, how well the paste releases from the aperture. The paste release, in turn, depends on the surface characteristics of the aperture wall and stencil foil. The recent introduction of new technology, nano-coating for both stencil and squeegee blades, has drawn the attention of many researchers. As the name implies, nano-coated stencils and blades are made by a conventional method such as laser-cut or electroformed then coated with nano-functional material to alter the surface characteristics. This study will evaluate nano-coated stencils for passive component printing, including 01005.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
Technical Library | 2017-10-19 01:17:56.0
Wetting balance testing has been an industry standard for evaluating the solderability of surface finishes on printed circuit boards (PCB) for many years. A Wetting Balance Curve showing Force as a function of Time, along with the individual data outputs "Time to Zero" T(0), "Time to Two-Thirds Maximum Force" T(2/3), and "Maximum Force" F(max) are usually used to evaluate the solderability performance of various surface finishes. While a visual interpretation of the full curve is a quick way to compare various test results, this method is subjective and does not lend itself readily to a rigorous statistical evaluation. Therefore, very often, when a statistical evaluation is desired for comparing the solderability between different surface finishes or different test conditions, one of the individual parameters is chosen for convenience. However, focusing on a single output usually doesn't provide a complete picture of the solderability of the surface finish being evaluated.In this paper, various models here-in labeled as "point" and "area" models are generated using the three most commonly evaluated individual outputs T(0), T(2/3), and F(max). These models have been studied to quantify how well each describes the full wetting balance curve. The solderability score (S-Score) with ranking from 0 to 10 were given to quantify the wetting balance curve as the result of the model study, which corresponds well with experimental results.
Technical Library | 2015-05-28 17:34:48.0
The printed circuit board assembly industry has long embraced the "Smaller, Lighter, Faster" mantra for electronic devices, especially in our ubiquitous mobile devices. As manufacturers increase smart phone functionality and capability, designers must adopt smaller components to facilitate high-density packaging. Measuring over 40% smaller than today's 0402M (0.4mmx0.2mm) microchip, the new 03015M (0.3mm×0.15mm) microchip epitomizes the bleeding-edge of surface mount component miniaturization. This presentation will explore board and component trends, and then delve into three critical areas for successful 03015M adoption: placement equipment, assembly materials, and process controls. Beyond machine requirements, the importance of taping specifications, component shape, solder fillet, spacing gap, and stencil design are explored. We will also examine how Adaptive Process Control can increase production yields and reduce defects by placing components to solder position rather than pad. Understanding the process considerations for 03015M component mounting today will help designers and manufacturers transition to successful placement tomorrow.
Technical Library | 2016-10-20 18:13:34.0
Pad cratering failure has emerged due to the transition from traditional SnPb to SnAgCu alloys in soldering of printed circuit assemblies. Pb-free-compatible laminate materials in the printed circuit board tend to fracture under ball grid array pads when subjected to high strain mechanical loads. In this study, two Pb-free-compatible laminates were tested, plus one dicycure non-Pb-free-compatible as control. One set of these samples were as-received and another was subjected to five reflows. It is assumed that mechanical properties of different materials have an influence on the susceptibility of laminates to fracture. However, the pad cratering phenomenon occurs at the layer of resin between the exterior copper and the first glass in the weave. Bulk mechanical properties have not been a good indicator of pad crater susceptibility. In this study, mechanical characterization of hardness and Young’s modulus was carried out in the critical area where pad cratering occurs using nano-indentation at the surface and in a cross-section. The measurements show higher modulus and hardness in the Pb-free compatible laminates than in the dicy-cured laminate. Few changes are seen after reflow – which is known to have an effect -- indicating that these properties do not provide a complete prediction. Measurements of the copper pad showed significant material property changes after reflow.
Technical Library | 2016-12-29 15:37:51.0
The reliabilities of the flux residue of electronic assemblies and semiconductor packages are attracting more and more attention with the adoption of no-clean fluxes by majority of the industry. In recent years, the concern of "partially activated" flux residue and their influence on reliability have been significantly raised due to the miniaturization along with high density design trend, selective soldering process adoption, and the expanded use of pallets in wave soldering process. When flux residue becomes trapped under low stand-off devices, pallets or unsoldered areas (e.g. selective process), it may contain unevaporated solvent, "live" activators and metal complex intermediates with different chemical composition and concentration levels depending on the thermal profiles. These partially-activated residues can directly impact the corrosion, surface insulation and electrochemical migration of the final assembly. In this study, a few application tests were developed internally to understand this issue. Two traditional liquid flux and two newly developed fluxes were selected to build up the basic models. The preliminary results also provide a scientific approach to design highly reliable products with the goal to minimize the reliability risk for the complex PCB designs and assembly processes. This paper was originally published by SMTA in the Proceedings of SMTA International
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