Technical Library | 2017-02-09 17:08:44.0
The SMT assembly world, especially within the commercial electronics realm, is dominated by no-clean solder paste technology. A solder paste flux residue that does not require removal is very attractive in a competitive world where every penny of assembly cost counts. One important aspect of the reliability of assembled devices is the nature of the no-clean solder paste flux residue. Most people in this field understand the importance of having a process that renders the solder paste flux residue as benign and inert as possible, thereby ensuring electrical reliability.But, of all the factors that play into the electrical reliability of the solder paste flux residue, is there any impact made by the age of the solder paste and how it was stored? This paper uses J-STD-004B SIR (Surface Insulation Resistance) testing to examine this question.
Technical Library | 2023-01-10 20:15:42.0
Over the past years there has been consistent growth in the use of electroless nickel / immersion gold (ENIG) as a final finish. The finish is now frequently being used for PBGA, CSP, QFP and COB and more recently gathered considerable interest as a low cost under-bump metallization for flip chip bumping application. One of the largest users for this finish has been the telecommunication industry, were millions of square meters of PCBs with ENIG have been successfully used. The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via thermal integrity. In addition the nickel layer offers advantages such as co-planarity, Al-wire bondability and the use as contact surface for keypads or contact switching. Especially those pads, which are not covered by solder need a protective coating in corrosive environment – such as high humidity or pollutant gas.
Technical Library | 2023-04-17 17:05:47.0
In an ideal world, manufacturing devices would work all of the time, however, every company receives customer returns for a variety of reasons. If these returned parts contributed to a fail, most companies will perform failure analysis (FA) on the returned parts to determine the root cause of the failure. Failure can occur for a multitude of reasons, for example: wear out, fatigue, design issues, manufacturing flaw or defect. This information is then used to improve the overall quality of the product and prevent reoccurrence. If no defect is found, it is possible that in fact the product has no defect. On the other hand, the defect could be elusive and the FA techniques insufficient to detect said deficiency. No-clean flux residues can cause intermittent or elusive, hard to find defects. In an attempt to understand the effects of no-clean flux residues from the secondary soldering and cleaning processes, a matrix of varying process and cleaning operation was investigated. Of special interest, traveling flux residues and entrapped residues were examined, as well as localized and batch cleaning processes. Various techniques were employed to test the remaining residues in order to assess their propensity to cause a latent failure. These techniques include Surface Insulation Resistance1 (SIR) testing at 40⁰C/90% RH, 5 VDC bias along with C32 testing and Ion Exchange Chromatography (IC). These techniques facilitate the assessment of the capillary effect the tight spacing these component structures have when flux residues are present. It is expected that dendritic shorting and measurable current leakage will occur, indicating a failing SIR test. However, since the residue resides under the discrete components, there will be no visual evidence of dendritic growth or metal migration.
Technical Library | 2007-08-28 20:18:06.0
A conformal coating is defined as a thin polymeric material which covers the surface of an electronic assembly. These coatings are used to provide an electrically insulative and environmentally protective seal or cover to a completed printed circuit board (PCB).
Technical Library | 1999-05-07 08:50:40.0
To enable transistor scaling into the 21st century, new solutions such as high dielectric constaConventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10mm in the 1970’s to a present day size of 0.1mm. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistorsnt materials for gate insulation and shallow, ultra low resistivity junctions need to be developed.
Technical Library | 2020-09-02 22:14:36.0
The demand for miniaturization and higher density electronic products has continued steadily for years, and this trend is expected to continue, according to various semiconductor technology and applications roadmaps. The printed circuit board (PCB) must support this trend as the central interconnection of the system. There are several options for fine line circuitry. A typical fine line circuit PCB product using copper foil technology, such as the modified semi-additive process (mSAP), uses a thin base copper layer made by pre-etching. The ultrathin copper foil process (SAP with ultrathin copper foil) is facing a technology limit for the miniaturization due to copper roughness and thickness control. The SAP process using sputtered copper is a solution, but the sputtering process is expensive and has issues with via plating. SAP using electroless copper deposition is another solution, but the process involved is challenged to achieve adequate adhesion and insulation between fine-pitch circuitries. A novel catalyst system--liquid metal ink (LMI)--has been developed that avoids these concerns and promotes a very controlled copper thickness over the substrate, targeting next generation high density interconnect (HDI) to wafer-level packaging substrates and enabling 5-micron level feature sizes. This novel catalyst has a unique feature, high density, and atomic-level deposition. Whereas conventional tin-palladium catalyst systems provide sporadic coverage over the substrate surface, the deposited catalyst covers the entire substrate surface. As a result, the catalyst enables improved uniformity of the copper deposition starting from the initial stage while providing higher adhesion and higher insulation resistance compared to the traditional catalysts used in SAP processes. This article discusses this new catalyst process, which both proposes a typical SAP process using the new catalyst and demonstrates the reliability improvements through a comparison between a new SAP PCB process and a conventional SAP PCB process.
Technical Library | 2023-03-16 19:07:51.0
HISTORY: * In the late 1970s an abrupt unpredictable loss of insulation resistance was observed in PCBs, which were subject to hostile climatic conditions of high relative humidity and temperature while having an applied voltage. * The loss of resistance, even leading to a short circuit was observed to be due to the growth of a subsurface filament from the anode to the cathode. * The term "Conductive Anodic Filamentation" (CAF) was coined.
Technical Library | 2015-05-21 18:46:31.0
In this work the reliability of an embedded planar capacitor laminate under temperature and voltage stress is investigated. The capacitor laminate consisted of an epoxy-BaTiO3 composite sandwiched between two layers of copper. The test vehicle with the embedded capacitors was subjected to a temperature of 125oC and a voltage bias of 200 V for 1000 hours. Capacitance, dissipation factor, and insulation resistance were monitored in-situ. Failed capacitors exhibited a sharp drop in insulation resistance, indicating avalanche breakdown. The decrease in the capacitance after 1000 hours was no more than 8% for any of the devices monitored. The decrease in the capacitance was attributed to delamination in the embedded capacitor laminate and an increase in the spacing between the copper layers.
Technical Library | 2015-03-26 19:16:03.0
Nickel-palladium-gold-finished terminals are susceptible to creep corrosion. Excessive creep corrosion can result in device failure due to insulation resistance loss between adjacent terminals. The mixed flowing gas test has been demonstrated to produce creep corrosion on parts with nickel-palladium-gold finished terminals. Conformal coats are often used to protect printed wiring assemblies from failure due to moisture and corrosion. However, coating may not be sufficient to protect lead terminations from failure.In this study, acrylic, silicone, urethane, parylene, and atomic layer deposit (ALD) coatings were examined for their effectiveness at preventing corrosion of nickel-palladium-gold-finished terminals.
Technical Library | 2019-08-15 13:31:52.0
Cracks in ceramic chip capacitors can be introduced at any process step during surface mount assembly. Thermal shock has become a "pat" answer for all of these cracks, but about 75 to 80% originate from other sources. These sources include pick and place machine centering jaws, vacuum pick up bit, board depanelization, unwarping boards after soldering, test fixtures, connector insulation, final assembly, as well as defective components. Each source has a unique signature in the type of crack that it develops so that each can be identified as the source of error.
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