Technical Library | 2023-02-13 18:56:42.0
This paper describes the results of an intensive whisker formation study on Pb-free assemblies with different levels of cleanliness. Thirteen types of as-received surface-mount and pin-through-hole components were cleaned and intentionally contaminated with solutions containing chloride, sulfate, bromide, and nitrate. Then the parts were assembled on double-sided boards that were also cleaned or intentionally contaminated with three fluxes having different halide contents. The assemblies were subjected to high-temperature/high-humidity testing (85_C/85% RH). Periodic examination found that contamination triggered whisker formation on both exposed tin and solder fillets. Whisker occurrence and parameters depending on the type and level of contamination are discussed. Cross-sections were used to assess the metallurgical aspects of whisker formation and the microstructural changes occurring during corrosion.
Technical Library | 1999-08-09 11:11:55.0
A great deal of controversy continues to surround the use of Hot Air Solder Leveling (HASL) in the production of printed circuit boards (PCBs). The financial burden, technological limitations and environmental issues surrounding the HASL process continue to grow. This requires an in-depth review by the printed circuit board manufacturing plant, as well as the assembly operation and instrument designers ( OEMs), to determine what alternative surface finishes are appropriate.
Technical Library | 2013-10-31 17:36:41.0
Multilayer printed circuit boards (PCBs) that utilize high performance materials are inherently far more challenging for a fabricator to build, due to significant material property differences over standard epoxy glass FR4. These unique material characteristics often require higher processing temperatures, special surface treatments (to aid in hole and surface plating), they possess different expansion properties, making layer-to-layer registration more difficult to control, and require many other unique considerations.
Technical Library | 2015-04-30 20:17:03.0
Higher-speed signal transmission is increasingly required on a printed circuit board to handle massive data in electronic systems. So, signal transmission loss of copper wiring on a printed circuit board has been studied. First, total signal loss was divided into dielectric loss and conductor loss quantitatively based on electromagnetic theory. In particular, the scattering loss due to surface roughness of copper foil has been examined in detail. And the usefulness of the copper foil with low surface roughness has been demonstrated.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2023-06-12 19:18:24.0
As any new technology emerges, increasing levels of refinement are required to facilitate the mainstream implementation and continual improvement processes. In the case of lead-free processing, the initial hurdles of alloy and chemistry selection are cleared on the first level, providing a base process. The understanding gained from early work on the base process leads to the next level of refinement in optimizing the primary factors that influence yield. These factors may include thermal profiles, PWB surface finishes, component metallization, solder mask selection or stencil design.
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2015-02-12 16:57:56.0
Electronic systems are known to be affected by the environmental and mechanical conditions, such as humidity, temperature, thermal shocks and vibration. These adverse environmental operating conditions, with time, could degrade the mechanical efficiency of the system and might lead to catastrophic failures.The aim of this study is to investigate the mechanical integrity of lead-free ball grid array (BGA) solder joints subjected to isothermal ageing at 150°C for up to 1000 hours. Upon ageing at 150°C the Sn-3.5Ag solder alloy initially age-softened for up to 200 hours. This behaviour was linked to the coarsening of grains. When aged beyond 200 hours the shear strength was found to increase up to 400 hours. This age-hardening was correlated with precipitation of hard Ag3Sn particles in Sn matrix. Further ageing resulted in gradual decrease in shear strength. This can be explained as the combined effect of precipitation coarsening and growth of intermetallic layer. The fractured surfaces of the broken solder balls were also investigated under a Scanning Electron Microscope. The shear failures were generally due to ductile fractures in bulk solders irrespective of the ageing time.
Technical Library | 2021-11-03 16:36:36.0
Laser reflow soldering is an important technology in electronic components processing. In this paper, we presented a simple but efficient method to achieve reflow soldering process with gradient energy band created by just two parallel mirrors. The detailed influence of the variety of optical parameters on the soldering process has been analyzed by using the finite element method. And the modulation of the optical parameters on reflow soldering parameters also has been demonstrated. In our experiment, one HR mirror and one-mirror with transmissivity of 10% have been used to create a gradient energy band with an incident laser power of 50W. In summary, both the simulations and the experiments show that the typical reflow soldering profile has been acquired by the optical system. The high quality joints on both the front and rear surface of the capacitor can be acquired by just one surface radiation of the optical system.
Technical Library | 2022-09-12 14:07:47.0
Unique component handling issues can arise when an assembly factory uses highly-moisture sensitive surface mount devices (SMDs). This work describes how the distribution of moisture within the molded plastic body of a SMD is an important variable for survivability. JEDEC/IPC [1] moisture level rated packages classified as Levels 4-5a are shown to require additional handling constraints beyond the typical out-of-bag exposure time tracking. Nitrogen or desiccated cabinet containment is shown as a safe and effective means for long-term storage provided the effects of prior out-of-bag exposure conditions are taken into account. Moisture diffusion analyses coupled with experimental verification studies show that time in storage is as important a variable as floor-life exposure for highly-moisture sensitive devices. Improvements in floor-life survivability can be obtained by a handling procedure that includes cyclic storage in low humidity containment. SMDs that have exceeded their floor-life limits are analyzed for proper baking schedules. Optimized baking schedules can be adopted depending on a knowledge of the exposure conditions and the moisture sensitivity level of the device.
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