Technical Library | 2020-03-26 14:55:29.0
This paper introduces line confocal technology that was recently developed to characterize 3D features of various surface and material types at sub-micron resolution. It enables automatic microtopographic 3D imaging of challenging objects that are difficult or impossible to scan with traditional methods, such as machine vision or laser triangulation.Examples of well-suited applications for line confocal technology include glossy, mirror-like, transparent and multi-layered surfaces made of metals (connector pins, conductor traces, solder bumps etc.), polymers (adhesives, enclosures, coatings, etc.), ceramics (components, substrates, etc.) and glass (display panels, etc.). Line confocal sensors operate at high speed and can be used to scan fast-moving surfaces in real-time as well as stationary product samples in the laboratory. The operational principle of the line confocal method and its strengths and limitations are discussed.Three metrology applications for the technology in electronics product manufacturing are examined: 1. 3D imaging of etched PCBs for micro-etched copper surface roughness and cross-sectional profile and width of etched traces/pads. 2. Thickness, width and surface roughness measurement of conductive ink features and substrates in printed electronics applications. 3. 3D imaging of adhesive dots and lines for shape, dimensions and volume in PCB and product assembly applications.
Technical Library | 2016-08-11 15:49:59.0
The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size, make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition, the low standoff between the die and interposer make it difficult to underfill. A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario, the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate. In this paper, we will discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do 2.5D assembly in an OSAT(Outsourced Assembly and Test) facility.
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