Technical Library | 2015-09-17 17:36:56.0
RoHS legislated restrictions on the materials used in electronics manufacture have imparted significant challenges on the electronics industry since their introduction in 2006. The greatest impacts have been felt by the mandated elimination of lead from electronic solder followed by the demand for the elimination of haloids from flame retardants used in traditional PCB laminates. In the years which have followed the electronics industry has been beset with a host of new challenges in its effort to comply. Failure mechanisms, both new and old, have surfaced which demand solution and the industry suppliers and manufacturing technologists have worked diligently to remedy those vexing faults through the development of a wide range of new materials and equipment for both board manufacture and assembly, along with modifications to the processes used in the manufacture and assembly of printed circuit boards.
Technical Library | 2018-11-20 21:33:57.0
There are several industry-accepted methods for determining the reliability of flux residues after assembly. The recommended methods of test sample preparation do not always closely mimic the thermal cycle experienced by an assembly. Therefore, extraction from actual assemblies has become a popular method of process control to assess consistency of post-reflow cleanliness. Every method of post-reflow flux residue characterization will depend on the reflow process followed to prepare the coupon.This investigation will focus on the effect of thermal conditions on the remainder of active ingredients in flux residues after assembly with no-clean solder pastes.
Technical Library | 2013-06-20 14:33:12.0
With today's consumer technologies driving the need for denser and more compact devices, the assembly process for surface mounted devices has becoming increasingly more difficult. With the mixture of components requiring a broader range of print deposition volume, various techniques are in use in an attempt to ensure consistent and appropriate paste volume is achieved. Some of these techniques include step etching a stencil locally on a targeted device, promoting electroformed smooth wall nickel stencils, through to laser cutting newer grade stencil materials. This paper focuses on the relevant attributes that affect the properties of solder paste release and introduces the effects of surface free energy with respect to key elements that make up the stencil printing process.
Technical Library | 2017-04-13 16:14:27.0
The drive to reduced size and increased functionality is a constant in the world of electronic devices. In order to achieve these goals, the industry has responded with ever-smaller devices and the equipment capable of handling these devices. The evolution of BGA packages and leadless devices is pushing existing technologies to the limit of current assembly techniques and materials.As smaller components make their way into the mainstream PCB assembly market, PCB assemblers are reaching the limits of Type 3 solder paste, which is currently in use by most manufacturers.The goal of this study is to determine the impact on solder volume deposition between Type 3, Type 4 and Type 5 SAC305 alloy powder in combination with stainless steel laser cut, electroformed and the emerging laser cut nano-coated stencils. Leadless QFN and μBGA components will be the focus of the test utilizing optimized aperture designs.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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