Technical Library | 2021-08-11 01:00:37.0
Conformal coatings and potting materials continue to create issues for the electronics industry. This webinar will dig deeper into the failure modes of these materials, specifically issues with Coefficient of Thermal Expansion (CTE), delamination, cracking, de-wetting, pinholes/bubbles and orange peel issues with conformal coatings and what mitigation techniques are available. Similarly, this webinar will look at the failure modes of potting materials, (e.g Glass Transition Temperature (Tg), PCB warpage, the effects of improper curing and potential methods for correcting these situations.
Technical Library | 2014-09-18 16:48:26.0
Two major drivers in electronic industry are electrical and mechanical miniaturization. Both induce major changes in the material selection as well as in the design. Nevertheless, the mechanical and thermal reliability of a Printed Circuit Board (PCB) has to remain at the same high level or even increase (e.g. multiple lead-free soldering). To achieve these reliability targets, extensive testing has to be done with bare PCB as well as assembled PCB. These tests are time consuming and cost intensive. The PCBs have to be produced, assembled, tested and finally a detailed failure analysis is required to be performed.This paper examines the development of our concept and has the potential to enable the prediction of the lifetime of the PCB using accelerated testing methods and finite element simulations.
Technical Library | 2019-05-15 22:26:02.0
As the demand for higher routing density and transfer speed increases, Via-In-Pad Plated Over (VIPPO) has become more common on high-end telecommunications products. The interactions of VIPPO with other features used on a PCB such as the traditional dog-bone pad design could induce solder joints to separate during the second and thereafter reflows. The failure has been successfully reproduced, and the typical failure signature of a joint separation has been summarized.To better understand the solder separation mechanism, this study focuses on designing a test vehicle to address the following three perspectives: PCB material properties, specifically the Z-direction or out-of-plane Coefficient of Thermal Expansion (CTE); PCB thickness and back drill depth; and quantification of the driving force magnitude beyond which the separation is due to occur.
Technical Library | 2019-10-16 23:18:15.0
Despite being a continuous subject of discussion, the existence of voids and their effect on solder joint reliability has always been controversial. In this work we revisit previous works on the various types of voids, their origins and their effect on thermo-mechanical properties of solder joints. We focus on macro voids, intermetallics micro voids, and shrinkage voids, which result from solder paste and alloy characteristics. We compare results from the literature to our own experimental data, and use fatigue-crack initiation and propagation theory to support our findings. Through a series of examples, we show that size and location of macro voids are not the primary factor affecting solder joint mechanical and thermal fatigue life. Indeed, we observe that when these voids area conforms to the IPC-A-610 (D or F) or IPC-7095A standards, macro voids do not have any significant effect on thermal cycling or drop shock performance.
Technical Library | 2024-07-24 00:51:44.0
A blade server system (BSS) utilizes voltage regulator modules (VRMs), in the form of quad flat no-lead (QFN) devices, to provide power distribution to various components on the system board. Depending on the power requirements of the circuit, these VRMs can be mounted as single devices or banked together. In addition, the power density of the VRM can be high enough to warrant heat dissipation through the use of a heat sink. Typically, at field conditions (FCs), the BSS are powered on and off up to four times per day, with their ambient temperature cycling between 258C and 808C. This cyclical temperature gradient drives inelastic strain in the solder joints due to the coefficient of thermal expansion (CTE) mismatch between the QFN and the circuit card. In addition, the heat sink, coupled with the QFN and the circuit card, can induce additional inelastic solder joint strain, resulting in early solder joint fatigue failure. To understand the effect of the heat sink mounting, a FEM (finite element model of four QFNs mounted to a BSS circuit card was developed. The model was exercised to calculate the maximum strain energy in a critical joint due to cyclic strain, and the results were compared for a QFN with and without a heat sink. It was determined that the presence of the heat sink did contribute to higher strain energy and therefore could lead to earlier joint failure. Although the presence of the heat sink is required, careful design of the mounting should be employed to provide lateral slip, essentially decoupling the heat sink from the QFN joint strain. Details of the modeling and results, along with DIC (digital image correlation) measurements of heat sink lateral slip, are presented.
Technical Library | 2022-10-11 20:29:31.0
Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantiication of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2014-10-30 01:48:43.0
The ultimate life of a microelectronics component is often limited by failure of a solder joint due to crack growth through the laminate under a contact pad (cratering), through the intermetallic bond to the pad, or through the solder itself. Whatever the failure mode proper assessments or even relative comparisons of life in service are not possible based on accelerated testing with fixed amplitudes, or random vibration testing, alone. Effects of thermal cycling enhanced precipitate coarsening on the deformation properties can be accounted for by microstructurally adaptive constitutive relations, but separate effects on the rate of recrystallization lead to a break-down in common damage accumulation laws such as Miner's rule. Isothermal cycling of individual solder joints revealed additional effects of amplitude variations on the deformation properties that cannot currently be accounted for directly. We propose a practical modification to Miner's rule for solder failure to circumvent this problem. Testing of individual solder pads, eliminating effects of the solder properties, still showed variations in cycling amplitude to systematically reduce subsequent acceleration factors for solder pad cratering. General trends, anticipated consequences and remaining research needs are discussed
Technical Library | 2023-02-13 19:14:03.0
Technology Focus: Develop and evaluate nanoparticle filled conformal coatings designed to provide long term whisker penetration resistance and coverage on tin rich metal surfaces prone to whisker growth in commercial lead-free electronics used in modern DoD systems. Research Objectives: Identify the fundamental mechanisms by which conformal coatings provide long-term tin whisker penetration resistance and inhibit nucleation/growth. Correlate mechanical properties and coverage thickness to whisker penetration resistance. Project Progress and Results: Functionalized nanosilica and non-functional nanoalumina enhanced polyurethane conformal coatings have shown improved spray coating coverage characteristics and crack resistance during thermal cycling fatigue testing. Lead-free assembly whisker mitigation validation testing is in process. Technology Transition: Current project partners provide coating materials to industry. SERDP test data will be considered during updates to the DoD adopted IPC standards for coating materials and coverage.
Technical Library | 2020-09-23 21:37:25.0
The need to minimise thermal damage to components and laminates, to reduce warpage-induced defects to BGA packages, and to save energy, is driving the electronics industry towards lower process temperatures. For soldering processes the only way that temperatures can be substantially reduced is by using solders with lower melting points. Because of constraints of toxicity, cost and performance, the number of alloys that can be used for electronics assembly is limited and the best prospects appear to be those based around the eutectic in the Bi-Sn system, which has a melting point of about 139°C. Experience so far indicates that such Bi-Sn alloys do not have the mechanical properties and microstructural stability necessary to deliver the reliability required for the mounting of BGA packages. Options for improving mechanical properties with alloying additions that do not also push the process temperature back over 200°C are limited. An alternative approach that maintains a low process temperature is to form a hybrid joint with a conventional solder ball reflowed with a Bi-Sn alloy paste. During reflow there is mixing of the ball and paste alloys but it has been found that to achieve the best reliability a proportion of the ball alloy has to be retained in the joint, particular in the part of the joint that is subjected to maximum shear stress in service, which is usually the area near the component side. The challenge is then to find a reproducible method for controlling the fraction of the joint thickness that remains as the original solder ball alloy. Empirical evidence indicates that for a particular combination of ball and paste alloys and reflow temperature the extent to which the ball alloy is consumed by mixing with the paste alloy is dependent on the volume of paste deposited on the pad. If this promising method of achieving lower process temperatures is to be implemented in mass production without compromising reliability it would be necessary to have a method of ensuring the optimum proportion of ball alloy left in the joint after reflow can be consistently maintained. In this paper the author explains how the volume of low melting point alloy paste that delivers the optimum proportion of retained ball alloy for a particular reflow temperature can be determined by reference to the phase diagrams of the ball and paste alloys. The example presented is based on the equilibrium phase diagram of the binary Bi-Sn system but the method could be applied to any combination of ball and paste alloys for which at least a partial phase diagram is available or could be easily determined.
