Technical Library | 2014-07-17 17:01:10.0
Embedded computing systems used in many military and avionics applications are trending toward higher heat fluxes, and as a result performance is being hindered by thermal limitations. This is intensified by the high ambient conditions experience by today’s modern warfighter. In many applications liquid cooling is replacing air flow through chassis for both thermal and environmental benefits(...) This paper outlines a series of passive thermal improvements which are easily integrated into legacy, or existing, systems and can provide a 3-4x increase in dissipated power.
Technical Library | 2013-02-08 22:56:47.0
Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.
Technical Library | 2013-08-22 14:28:58.0
Tin-rich solders are widely applied in the electronic industry in the majority of modern printed circuit boards (PCBs). Because the use of lead-tin solders has been banned in the European Union since 2006, the problem of the bridging of adjacent conductors due to tin whisker growth (limited before by the addition of Pb) has been reborn. In this study tin alloys soldered on glass-epoxy laminate (typically used for PCBs) are considered. Scanning ion microscopy with Focused Ion Beam (FIB) system and energy-dispersive X-ray spectroscopy (EDXS) were used to determine correlations between spatial non-uniformities of the glass-epoxy laminate, the distribution of intermetallic compounds and whisker growth.
Technical Library | 2020-05-26 22:28:56.0
Both the number and the variants of Ball Grid Array packages (BGAs) are tending to increase on network Printed Board Assemblies (PBAs)with sizes ranging from a few mm die size Wafer Level Packages (WLPs) with low ball count up to large multi-die System-in-Package (SiP) BGAs with 60-70 mm side lengths and thousands of I/Os.
Technical Library | 2022-10-04 16:43:10.0
In this paper I will discuss the different methods and equipment used to detect counterfeit electronic parts, specifically integrated circuits as well as demonstrate some of the "red flags" that help to identify a part as being suspected counterfeit. We will begin with the initial receipt of the parts and the examination of the outer packaging, the basic visual inspection of the parts, the visual inspection and documentation at high magnification, permanency marking, blacktop test, scrape test, XRF (RoHS), decapsulation, X-ray, basic electrical testing, C-SAM, full function testing and limited function testing.
Technical Library | 2014-10-30 01:48:43.0
The ultimate life of a microelectronics component is often limited by failure of a solder joint due to crack growth through the laminate under a contact pad (cratering), through the intermetallic bond to the pad, or through the solder itself. Whatever the failure mode proper assessments or even relative comparisons of life in service are not possible based on accelerated testing with fixed amplitudes, or random vibration testing, alone. Effects of thermal cycling enhanced precipitate coarsening on the deformation properties can be accounted for by microstructurally adaptive constitutive relations, but separate effects on the rate of recrystallization lead to a break-down in common damage accumulation laws such as Miner's rule. Isothermal cycling of individual solder joints revealed additional effects of amplitude variations on the deformation properties that cannot currently be accounted for directly. We propose a practical modification to Miner's rule for solder failure to circumvent this problem. Testing of individual solder pads, eliminating effects of the solder properties, still showed variations in cycling amplitude to systematically reduce subsequent acceleration factors for solder pad cratering. General trends, anticipated consequences and remaining research needs are discussed
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
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