Technical Library | 2017-08-31 13:43:48.0
Wire bonded packages using conventional copper leadframe have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – non-stick on pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction
Technical Library | 2017-10-12 15:45:25.0
The risk associated with whisker growth from pure tin solderable terminations is fully mitigated when all of the pure tin is dissolved into tin-lead solder during SMT reflow. In order to take full advantage of this phenomenon, it is necessary to understand the conditions under which such coverage can be assured. A round robin study has been performed by IPC Task group 8-81f, during which identical sets of test vehicles were assembled at multiple locations, in accordance with IPC J-STD-001, Class 3. All of the test vehicles were analyzed to determine the extent of complete tin dissolution on a variety of component types. Results of this study are presented together with relevant conclusions and recommendations to guide high reliability end-users on the applicability and limitations of this mitigation strategy.
Technical Library | 2018-02-28 22:28:30.0
Circuit functional density requirements continue to drive innovative approaches to high performance packaging. Some new approaches include; aggressive space reduction, embedded solutions, and those that offer some form of risk reduction and rework potential are now options that are being explored by customers. Requirements for assembly of these types of packages necessitate the deposition of solder paste and assembly of components into cavities of the substrates to gain z-axis density as well as area functional density. Advances in the fabrication of PWB’s with cavities using newly developed laser micro-fabrication processes along with increased circuit pitch density of 50 micron lines and spaces permit new applications for high performance electronic substrates. First published at SMTA Pan Pacific Symposium
Technical Library | 2019-02-06 22:02:08.0
The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods, with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired, testing a variety of laminate materials (standard volume production with UL approval, low loss, and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified, as well as possible correlations or relationships among these higher speed test methods.
Technical Library | 2019-07-23 22:33:47.0
The Quad Flat Pack No Leads (QFN) style of leadless packaging [also known as a Land Grid Array (LGA)] is rapidly increasing in us e for wireless, automotive, telecom and many other areas becaus e of its low cost, low stand-off height and excellent thermal and electri cal properties. With the implementation of any new package type, there is always a learning curve for its use in design and processing as well as for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. Therefore, this paper will provide examples of the common process defects that can be seen with QFNs /LGAs when using optical and x-ray inspection as part of manufacturing quality control. Results of trials conducted on four PCB finishes and using vapour phase and convection reflow will be discussed.
Technical Library | 2020-03-19 00:23:15.0
In this study, the question was how to perform statistically reliable robust- ness tests for the non-contact drop-on-demand printing of functional fluids, such as solder paste and conductive adhesives. The goal of this study was to develop a general method for hypothesis testing when robustness tests are performed. The main problem was to determine if there was a statistical difference between two means or proportions of jet printing devices. In this study, an example of jetting quality variation was used when comparing two jet printing ejector types that differ slightly in design. We wanted to understand if the difference in ejector design can impact jetting quality by performing robustness tests. and thus answer the question, "Can jetting differences be seen between ejector design 1 and design 2"?
Technical Library | 2020-04-08 22:57:04.0
Flexible hybrid electronics (FHE), designed in wearable and implantable configurations, have enormous applications in advanced healthcare, rapid disease diagnostics, and persistent human-machine interfaces. Soft, contoured geometries and time-dynamic deformation of the targeted tissues require high flexibility and stretchability of the integrated bioelectronics. Recent progress in developing and engineering soft materials has provided a unique opportunity to design various types of mechanically compliant and deformable systems. Here, we summarize the required properties of soft materials and their characteristics for configuring sensing and substrate components in wearable and implantable devices and systems. Details of functionality and sensitivity of the recently developed FHE are discussed with the application areas in medicine, healthcare, and machine interactions. This review concludes with a discussion on limitations of current materials, key requirements for next generation materials, and new application areas.
Technical Library | 2021-01-21 02:04:27.0
Traditional single level microvia structures are generally considered the most robust type of interconnection within a printed wire board (PWB) substrate. The rapid implementation of HDI technology now commonly requires between 2, 3 or 4 levels of microvias sequentially processed into the product. Recent OEM funded reliability testing has confirmed that by increasing the levels (stack height) these structures are proving less reliable, when compared to their single or double level counterparts. Recently false positive results have been recorded on products tested with traditional thermal shock testing methodology (cycling between -40°C and 125°C, or 145°C). A number of companies are incurring product failures resulting in increased costs associated with replacing the circuit boards, components and added labour.
Technical Library | 2023-04-25 22:03:25.0
This report hopes to achieve several goals: 1. Determine the link between bare PWB contamination, soldered assembly contamination and long-term product reliability. 2. Establish measurable limits for bare PWB cleanliness as well as process control limits for both an aqueous as well as a water-soluble soldering process. 3. Determine whether there is any correlation between common, industry-accepted rose/modified rose (omegameter/ionograph type) testing and long term product reliability. 4. Determine the effect PWB plating finish (HASL, Immersion Silver and Cu OSP) has on both bare PWB contamination as well as soldered assembly in a no clean and water soluble process. 5. Determine whether there is a link between percentage of saponifier used to wash soldered assemblies and long-term reliability. 6. Establish a more cost-effective test for manufacturers to use as a process-monitoring tool.
Technical Library | 2019-10-16 23:18:15.0
Despite being a continuous subject of discussion, the existence of voids and their effect on solder joint reliability has always been controversial. In this work we revisit previous works on the various types of voids, their origins and their effect on thermo-mechanical properties of solder joints. We focus on macro voids, intermetallics micro voids, and shrinkage voids, which result from solder paste and alloy characteristics. We compare results from the literature to our own experimental data, and use fatigue-crack initiation and propagation theory to support our findings. Through a series of examples, we show that size and location of macro voids are not the primary factor affecting solder joint mechanical and thermal fatigue life. Indeed, we observe that when these voids area conforms to the IPC-A-610 (D or F) or IPC-7095A standards, macro voids do not have any significant effect on thermal cycling or drop shock performance.
