Technical Library | 2019-07-23 22:33:47.0
The Quad Flat Pack No Leads (QFN) style of leadless packaging [also known as a Land Grid Array (LGA)] is rapidly increasing in us e for wireless, automotive, telecom and many other areas becaus e of its low cost, low stand-off height and excellent thermal and electri cal properties. With the implementation of any new package type, there is always a learning curve for its use in design and processing as well as for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. Therefore, this paper will provide examples of the common process defects that can be seen with QFNs /LGAs when using optical and x-ray inspection as part of manufacturing quality control. Results of trials conducted on four PCB finishes and using vapour phase and convection reflow will be discussed.
Technical Library | 2014-08-28 17:09:23.0
The fastest growing package types in the electronics industry today are Bottom Termination Components (BTCs). While the advantages of BTCs are well documented, they pose significant reliability challenges to users. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies. This is especially true for new component packaging like BTCs. Obtaining relevant information can be difficult since information is often segmented and the focus is on design opportunities not on reliability risks (...)Commonly used conformal coating and potting processes have resulted in shortened fatigue life under thermal cycling conditions. Why do conformal coating and potting reduce fatigue life? This paper details work undertaken to understand the mechanisms underlying this reduction. Verification and determination of mechanical properties of some common materials are performed and highlighted. Recommendations for material selection and housing design are also given.
Technical Library | 2017-10-12 15:45:25.0
The risk associated with whisker growth from pure tin solderable terminations is fully mitigated when all of the pure tin is dissolved into tin-lead solder during SMT reflow. In order to take full advantage of this phenomenon, it is necessary to understand the conditions under which such coverage can be assured. A round robin study has been performed by IPC Task group 8-81f, during which identical sets of test vehicles were assembled at multiple locations, in accordance with IPC J-STD-001, Class 3. All of the test vehicles were analyzed to determine the extent of complete tin dissolution on a variety of component types. Results of this study are presented together with relevant conclusions and recommendations to guide high reliability end-users on the applicability and limitations of this mitigation strategy.
Technical Library | 2023-05-02 19:03:34.0
The demand for 0201 components in consumer products will increase sharply over the next few years due to the need for miniaturization. It is predicted that over 20 billion 0201 components will be used in more than one billion cell phones worldwide by the year 2003. Therefore, research and development on 0201 assembly is becoming a very hot topic. The first step to achieve a successful assembly process is to obtain a good PCB design for 0201 packages. This paper presents the data and criteria of PCB design for 0201 packages, including the pad design for 0201 components, and the minimum pad spacing or component clearance between 0201 components or between 0201 and other components. A systematic study on pad design and pad spacing was undertaken, using two test vehicles and three Design of Experiments (DOEs). In the first DOE, 2 out of 18 types of 0201 pad designs were selected based on process yield. The second DOE was focused on pad spacing, including 10mil, 8mil, 6mil and 4mil. The third experiment was final optimization, using two types of optimized pad designs with 10mil, 8mil and 6mil pad spacing. Through the above experiments, the design guideline for PCB layout for 0201 packages and the assembly process capability are identified.
Technical Library | 2011-10-20 22:03:30.0
Results of FEM modelling of thermal stress analysis in printed circuit boards are given in the article. It is shown that thermal stress alone is not solely caused by differences in coefficients of thermal expansion of individual layers. The emergence of thermal stress is subject to both the layered structure of the wall and given boundary conditions, as well as the existence of a temperature gradient in the direction normal to the surface of the wall. A practical application focuses on the issue of recycling of PCB with the effort to achieve separation of layers due to thermal stress. Role modelling of thermal stress in this area lies in predicting the possibility of separation, depending on the type of thermal stress and material parameters.
Technical Library | 2013-08-01 13:17:44.0
Electronic industry uses a number of metallic materials in various forms. Also new materials and technology are introduced all the time for increased performance. In recent years, corrosion of electronic systems has been a significant issue. Multiplicity of materials used is one reason limiting the corrosion reliability. However, the reduced spacing between components on a printed circuit board (PCB) due to miniaturization of device is another factor that has made easy for interaction of components in corrosive environments. Presently the knowledge on corrosion issues of electronics is very limited. This paper reviews briefly the materials used in electronic systems, factors influencing corrosion, types of corrosion observed in electronics, and testing methods.
Technical Library | 2021-10-20 18:21:06.0
The solderability of the SAC305 alloy in contact with printed circuit boards (PCB) having different surface finishes was examined using the wetting balance method. The study was performed at a temperature of 260 _C on three types of PCBs covered with (1) hot air solder leveling (HASL LF), (2) electroless nickel immersion gold (ENIG), and (3) organic surface protectant (OSP), organic finish, all on Cu substrates and two types of fluxes (EF2202 and RF800). The results showed that the PCB substrate surface finish has a strong effect on the value of both the wetting time t0 and the contact angle h. The shortest wetting time was noted for the OSP finish (t0 = 0.6 s with EF2202 flux and t0 = 0.98 s with RF800 flux), while the ENIG finish showed the longest wetting time (t0 = 1.36 s with EF2202 flux and t0 = 1.55 s with RF800 flux). The h values calculated from the wetting balance tests were as follows: the lowest h of 45_ was formed on HASL LF (EF2202 flux), the highest h of 63_ was noted on the OSP finish, while on the ENIG finish, it was 58_ (EF2202 flux). After the solderability tests, the interface characterization of cross-sectional samples was performed by means of scanning electron microscopy coupled with energy dispersive spectroscopy.
Technical Library | 2015-07-14 13:19:10.0
Bottom terminated components (BTC) are leadless components where terminations are protectively plated on the underside of the package. They are all slightly different and have different names, such as QFN (quad flat no lead), DFN (dual flat no lead), LGA (land grid array) and MLF (micro lead-frame. BTC assembly has increased rapidly in recent years. This type of package is attractive due to its low cost and good performance like improved signal speeds and enhanced thermal performance. However, bottom terminated components do not have any leads to absorb the stress and strain on the solder joints. It relies on the correct amount of solder deposited during the assembly process for having a good solder joint quality and reliable reliability. Voiding is typically seen on the BTC solder joint, especially on the thermal pad of the component. Voiding creates a major concern on BTC component’s solder joint reliability. There is no current industry standard on the voiding criteria for bottom terminated component. The impact of voiding on solder joint reliability and the impact of voiding on the heat transfer characteristics at BTC component are not well understood. This paper will present some data to address these concerns.
Technical Library | 2021-11-17 18:53:50.0
The demand for product miniaturization, especially in the handheld device area, continues to challenge the board assembly industry. The desire to incorporate more functionality while making the product smaller continues to push board design to its limit. It is not uncommon to find boards with castle-like components right next to miniature components. This type of board poses a special challenge to the board assemblers as it requires a wide range of paste volume to satisfy both small and large components. One way to address the printing challenge is to use creative stencil design to meet the solder paste requirement for both large and small components. ... The most important attribute of a stencil is its release characteristic. In other words, how well the paste releases from the aperture. The paste release, in turn, depends on the surface characteristics of the aperture wall and stencil foil. The recent introduction of new technology, nano-coating for both stencil and squeegee blades, has drawn the attention of many researchers. As the name implies, nano-coated stencils and blades are made by a conventional method such as laser-cut or electroformed then coated with nano-functional material to alter the surface characteristics. This study will evaluate nano-coated stencils for passive component printing, including 01005.
Technical Library | 2017-01-24 02:15:49.0
Basic performance of PCB (Printed Circuit Board) depends on the performance of substrate material. In order to improve the performance of PCB, you have to increase the performance of PCB substrate material first. This article introduces how to chose PCB substrate material for your custom PCB project from multiple perspectives.
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