Technical Library | 2019-05-08 21:52:28.0
Cold ball pull testing is used to validate the resistance of PCB pad cratering for the different ultra-low loss dielectrics materials (Dk=3~4.2 and Df
Technical Library | 2018-04-18 23:55:01.0
Higher functionality, higher performance and higher reliability with smaller real estate are the mantras of any electronic device and the future guarantees more of the same. In order to achieve the requirements of these devices, designs must incorporate fine line and via pitch while maintain good circuitry adhesion at a smooth plating-resin interface to improve signal integrity. The Semi-Additive Process (SAP) is a production-proven method used on low dielectric loss tangent (Df) build-up materials that enables the manufacture of ultra-fine circuitry. (...) This paper will discuss a new SAP process for low loss build-up materials with low desmear roughness (Ra= 40-100 nm) and excellent adhesion (610-680 gf/cm) at various processing conditions. Along with the process flow, the current work will also present results and a discussion regarding characterization on the morphology and composition of resin and/or metal plating surfaces using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX), surface roughness analysis, plating-resin adhesion evaluation from 90o peel tests
Technical Library | 2015-04-30 20:17:03.0
Higher-speed signal transmission is increasingly required on a printed circuit board to handle massive data in electronic systems. So, signal transmission loss of copper wiring on a printed circuit board has been studied. First, total signal loss was divided into dielectric loss and conductor loss quantitatively based on electromagnetic theory. In particular, the scattering loss due to surface roughness of copper foil has been examined in detail. And the usefulness of the copper foil with low surface roughness has been demonstrated.
Technical Library | 1999-05-07 08:50:40.0
To enable transistor scaling into the 21st century, new solutions such as high dielectric constaConventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10mm in the 1970’s to a present day size of 0.1mm. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistorsnt materials for gate insulation and shallow, ultra low resistivity junctions need to be developed.
Technical Library | 2010-10-28 01:27:38.0
Optical waveguides based on organic materials have been fabricated in a laboratory environment but the scaling and manufacturing processes needed to produce these waveguides have been scant. The volume production of low loss organic waveguides in a conven
Technical Library | 2019-02-13 13:45:11.0
Development of information and telecommunications network is outstanding in recent years, and it is required for the related equipment such as communication base stations, servers and routers, to process huge amount of data in no time. As an electrical signal becomes faster and faster, how to prevent signal delay by transmission loss is a big issue for Printed Circuit Boards (PCB) loaded on such equipments. There are two main factors as the cause of transmission loss; dielectric loss and conductor loss. To decrease the dielectric loss, materials having low dielectric constant and low loss tangent have been developed. On the other hand, reducing the surface roughness of the copper foil itself to be used or minimizing the surface roughness by modifying surface treatment process of the conductor patterns before lamination is considered to be effective in order to decrease the conductor loss. However, there is a possibility that reduction in the surface roughness of the conductor patterns will lead to the decrease in adhesion of conductor patterns to dielectric resin and result in the deterioration of reliability of PCB itself. In this paper, we will show the evaluation results of adhesion performance and electrical properties using certain type of dielectric material for high frequency PCB, several types of copper foil and several surface treatment processes of the conductor patterns. Moreover, we will indicate a technique from the aspect of surface treatment process in order to ensure reliability and, at the same time, to prevent signal delay at the signal frequency over 20 GHz.
Technical Library | 2021-08-18 01:27:15.0
The growing interest towards thinner and conformable electronic systems has attracted significant attention towards flexible hybrid electronics (FHE). Thin chip-foil packages fabricated by integrating ultra-thin monocrystalline silicon integrated circuits (ICs) on/in flexible foils have the potential to deliver high performance electrical functionalities at very low power requirements while being mechanically flexible.
Fraunhofer EMFT Research Institution for Microsystems and Solid State Technologies
Technical Library | 2012-06-27 18:26:34.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. Signal integrity analysis has shown that printed circuit board (PCB) insertion loss is a key factor affecting high speed channel performance. Determining and controlling PCB inser
Technical Library | 2012-11-01 20:54:49.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. The continuous progression toward portable, high frequency microelectronic systems has placed high demands on material performance, notably low dielectric constants (Dk), low loss tangent (Df), low moisture uptake, and good thermal stability. Epoxy resins are the workhorses of the electronic industry. Significant performance enhancements have been obtained through the use of PPE telechelic macromonomers with epoxy resins. However, there is a ceiling on the performance obtainable from epoxy-based resins. Therefore, non-epoxy based dielectric materials are used to fulfill the need for higher performance.
Technical Library | 2019-02-06 22:02:08.0
The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods, with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired, testing a variety of laminate materials (standard volume production with UL approval, low loss, and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified, as well as possible correlations or relationships among these higher speed test methods.
