Technical Library | 2017-09-25 10:36:52.0
Laser wire stripping was developed by NASA in the 1970s as part of the Space Shuttle program. The technology made it possible to use smaller sized wires with thinner insulations, without risk of the damage that can be caused by traditional mechanical wire stripping methods. Laser wire stripping technology was commercialized in the 1990s and was initially used for aerospace and defense applications. Laser wire stripping then grew significantly when the consumer electronics market exploded as lasers became the only stripping solution for the tiny data cables found in laptops, mobile phones and other consumer electronics products. Another large industry that has adopted laser wire stripping methods, and for good reason, is high-end medical device manufacturing.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
Technical Library | 2016-11-10 08:56:54.0
It goes without saying that every manufacturer wants to ensure they are producing a quality product. Standards and specifications from various organizations provide a guideline from which manufacturers can measure different areas of quality, while also providing the end user with the reassurance that they are purchasing a trustworthy, long-lasting product. Within the wire processing industry there are many standards that manufacturers may choose or be required to adhere to. These standards and specifications are constantly evolving and increasing in detail, especially as monitoring technology improves.
Technical Library | 2010-08-05 18:39:39.0
Variability analysis is important in successfully deploying multi-gigabit backplane printed wiring boards (PWBs) with growing numbers of high-speed SerDes links. We discuss the need for large sample sizes to obtain accurate variability estimates of SI me
Technical Library | 2009-01-01 16:37:38.0
Recent technology advancement has enabled enhancement in PWB electrical performance and wiring density. These innovations have taken the form of improved materials, novel PWB interconnect structures, and manufacturing technology. One such advancement is Z-axis conductive interconnect. The Z-interconnect technology involves building mini-substrates of 2 or 3 layers each, then assembling several mini-substrates together using conductive paste.
Technical Library | 2013-06-05 14:09:42.0
Quality standards are getting tougher each year. In these difficult times, wire harness manufacturers are looking to expand business in their existing markets and are looking for new markets. The following article will compare and contrast the current quality standards that are most commonly used today. It will review proper measurement techniques, discuss some trends in crimp quality, and address methods to improve efficiency in quality data collection.
Technical Library | 2022-02-21 19:49:16.0
The ability to undertake non-destructive testing on semiconductor devices, during both their manufacture and their subsequent use in printed circuit boards (PCBs), has become ever more important for checking product quality without compromising productivity. The use of x-ray inspection not only provides a potentially non-destructive test but also allows investigation within optically hidden areas, such as the wire bonding within packages and the quality of post solder reflow of area array devices (e.g. BGAs, CSPs and flip chips).
Technical Library | 2014-11-28 15:55:13.0
A soldering alloy composition Sn40-Bi60 has been manufactured by quenching method to achieve the both cast and wire shape. Differential scanning calorimetric (DSC) was done to study the melting behavior for a large portion of the alloy melts sharply at a approximately 136 C0 ,the melting point of Sn-Bi. X-Ray diffraction and optical microscopy were used to analyzed its microstructure characterization. The hardness of the alloys has been tested and find at a value 2 HRB as ductile form.
Technical Library | 2016-11-30 15:53:15.0
The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.
Technical Library | 2013-03-14 17:19:28.0
Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings.
