Technical Library: void on qfn pin (Page 1 of 1)

The Morphology Evolution and Voiding of Solder Joints on QFN Central Pads with a Ni/Au Finish

Technical Library | 2012-10-18 21:58:51.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish.

Agilent Technologies, Inc.

THE IMPACT OF VIA AND PAD DESIGN ON QFN ASSEMBLY

Technical Library | 2024-07-24 01:18:03.0

Quad Flat No-Lead (QFN) packages has become very popular in the industry and are widely used in many products. These packages have different size and pin counts, but they have a common feature: thermal pad at the bottom of device. The thermal pad of the leadless QFN provides efficient heat dissipation from the component to PCB. In many cases, arrays of the thermal via under the component is used to dissipate heat from the device. However, thermal vias can create more voids or result in solder protrusion onto the secondary side.

Flex (Flextronics International)

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