Technical Library | 2016-08-11 15:49:59.0
The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size, make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition, the low standoff between the die and interposer make it difficult to underfill. A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario, the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate. In this paper, we will discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do 2.5D assembly in an OSAT(Outsourced Assembly and Test) facility.
Technical Library | 2020-09-02 22:02:13.0
With the adoption of Wafer Level Packages (WLP) in the latest generation mobile handsets, the Printed Circuit Board (PCB) industry has also seen the initial steps of High Density Interconnect (HDI) products migrating away from the current subtractive processes towards a more technically adept technique, based on an advanced modified Semi Additive Process (amSAP). This pattern plate process enables line and space features in the region of 20um to be produced, in combination with fully filled, laser formed microvias. However, in order to achieve these process demands, a step change in the performance of the chemical processes used for metallization of the microvia is essential. In the electroless Copper process, the critical activator step often risks cross contamination by the preceding chemistries. Such events can lead to uncontrolled buildup of Palladium rich residues on the panel surface, which can subsequently inhibit etching and lead to short circuits between the final traces. In addition, with more demands being placed on the microvia, the need for a high uniformity Copper layer has become paramount, unfortunately, as microvia shape is often far from ideal, the deposition or "throw" characteristics of the Copper bath itself are also of critical importance. This "high throwing power" is influential elsewhere in the amSAP technique, as it leads to a thinner surface Copper layer, which aids the etching process and enables the ultra-fine features being demanded by today's high end PCB applications. This paper discusses the performance of an electroless Copper plating process that has been developed to satisfy the needs of challenging amSAP applications. Through the use of a radical predip chemistry, the formation, build up and deposition of uncontrolled Pd residues arising from activator contamination has been virtually eradicated. With the adoption of a high throwing power Copper bath, sub 30um features are enabled and microvia coverage is shown to be greatly improved, even in complex via shapes which would otherwise suffer from uneven coverage and risk premature failure in service. Through a mixture of development and production data, this paper aims to highlight the benefits and robust performance of the new electroless Copper process for amSAP applications
| 1 |
winsouce.jpg)
.gif)
