Technical Library | 2011-04-07 14:50:29.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry nowadays. This package offers a number of benefits including (1) small size, such as a near die-sized footprint, thin profile, and light weight; (2) easy PCB t
Technical Library | 2008-02-04 12:13:38.0
Engineers are always striving to make a lighter, faster and stronger PCB. In order to achieve their designs, engineers must turn to alternative materials to enhance their designs. There are many materials that allow for thermal, coefficient of thermal expansion (CTE) and rigidity. Many times if a material enables an engineer to have CTE they will have to sacrifice thermal. Currently carbon composite laminates are being used in order to achieve an ideal PCB with thermal, CTE and rigidity with almost no weight premiums.
Technical Library | 2024-07-24 01:04:35.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints.
Technical Library | 2021-12-16 01:45:05.0
In the 1990's, both BGA (Ball Grid Array) and CSP (Chip Size Package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (Surface Mount Device) from the I 980's and THD (Through-Hole mount Device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability.
Technical Library | 2021-06-07 19:06:32.0
The technological growth of the last decades has brought many improvements in daily life, but also concerns on how to deal with electronic waste. Electrical and electronic equipment waste is the fastest-growing rate in the industrialized world. One of the elements of electronic equipment is the printed circuit board (PCB) and almost every electronic equipment has a PCB inside it. While waste PCB (WPCB) recycling may result in the recovery of potentially precious materials and the reuse of some components, it is a challenging task because its composition diversity requires a cautious pre-processing stage to achieve optimal recycling outcomes. Our research focused on proposing a method to evaluate the economic feasibility of recycling integrated circuits (ICs) from WPCB. The proposed method can help decide whether to dismantle a separate WPCB before the physical or mechanical recycling process and consists of estimating the IC area from a WPCB, calculating the IC's weight using surface density, and estimating how much metal can be recovered by recycling those ICs. To estimate the IC area in a WPCB, we used a state-of-the-art object detection deep learning model (YOLO) and the PCB DSLR image dataset to detect the WPCB's ICs. Regarding IC detection, the best result was obtained with the partitioned analysis of each image through a sliding window, thus creating new images of smaller dimensions, reaching 86.77% mAP. As a final result, we estimate that the Deep PCB Dataset has a total of 1079.18 g of ICs, from which it would be possible to recover at least 909.94 g of metals and silicon elements from all WPCBs' ICs. Since there is a high variability in the compositions of WPCBs, it is possible to calculate the gross income for each WPCB and use it as a decision criterion for the type of pre-processing.
Technical Library | 2015-12-31 15:19:28.0
Today's consumer electronic product are characterized by miniatuization, portability and light weight with high performance, especially for 3G mobile products. In the future more fine pitch CSPs (0.4mm) component will be required. However, the product reliability has been a big challenge with the fine pitch CSP. Firstly, the fine pitch CSPs are with smaller solder balls of 0.25mm diameter or even smaller. The small solder ball and pad size do weaken the solder connection and the adhesion of the pad and substrate, thus the pad will peel off easily from the PCB substrate. In addition, miniature solder joint reduce the strength during mechanical vibration, thermal shock, fatigue failure, etc. Secondly, applying sufficient solder paste evenly on the small pad of the CSP is difficult because stencil opening is only 0.25mm or less. This issue can be solved using the high end type of stencil such as Electroforming which will increase the cost.
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