Technical Library | 2007-01-31 14:10:17.0
This white paper is suitable for both new and experienced users. It is a practical education in the use and misuse of auger valves for solder paste dispensing.
Technical Library | 2011-03-16 20:09:11.0
The backplane is the key component in any system architecture. The sooner one considers the backplane’s physical architecture near the beginning of a project, the more successful the project will be. This white paper introduces the concept of a backplane
Technical Library | 2019-06-03 21:07:34.0
The objective of this White Paper is to provide users of the above products in the electronics industry a clear understanding of the different types of stencil cleaning paper/fabrics that are currently available. Fine pitch applications are more the norm now and so the performance of stencil cleaning rolls is more critical than ever before. This White Paper will give solder paste stencil printing engineers and purchasing professionals an insight into the main products on the market, thereby enabling them to make informed decisions.
Technical Library | 2023-12-26 17:50:54.0
In this white paper, we discuss the pros and cons of five analytical techniques when applied to residue analysis on electronic assemblies. We evaluate the following for their application and limitations for analyzing both visible and invisible residues: FITR, SEM/EDX, XRF, Ion Chromatography, and ROSE
Technical Library | 2016-09-19 20:26:36.0
This white paper seeks to set out the value of a ‘smarter’ approach to the reflow process and how a more intelligent oven can offer real added value and performance to the entire line. It also lays out some of the criteria that is important when selecting smart equipment for a smart process, that conforms to, and is ready for, IoM or Industry 4.0
Technical Library | 2023-02-15 16:00:16.0
With regard to potting, the design of electronic assemblies and components has a significant impact on economical and sustainable production. Key aspects in this respect are pottability, material use, cycle times, quality and the process technology needed. Optimized, bubble-free potting contributes greatly to the function and longevity of products. It is best practice during the design and development phases therefore to follow the potting tips contained in this White Paper.
Technical Library | 2024-03-20 13:37:18.0
Effective and reliable dispensing is based primarily on process technology that has been perfectly set up for the specific project. Anyone tasked with planning dispensing systems and responsible for the processes should know the principles and key factors involved so that the dispensing processes can be successfully implemented in cooperation with system and material partners. This White Paper explains the relevant aspects of process technology and provides valuable practical tips.
Technical Library | 2013-06-27 14:00:27.0
While IC level ESD design and the necessary protection levels are well understood, system ESD protection strategy and design efficiency have only been dealt with in an ad hoc manner. This is most obvious when we realize that a consolidated approach to system level ESD design between system manufacturers and chip suppliers has been rare. This White Paper discusses these issues in the open for the first time, and offers new and relevant insight for the development of efficient system level ESD design.
Technical Library | 2022-09-29 14:08:42.0
Electronic vehicles, devices and components must not overheat, otherwise they may fail to operate correctly. Thermal management is a major technical challenge as components are getting smaller, power densities are increasing and demands on robustness and reliability are becoming more stringent. To prevent power losses or defects resulting from overheating, liquid thermal interface materials (TIMs) are being increasingly used to dissipate their heat. This White Paper discusses the aspects that need to be taken into account when dispensing these mostly highly viscous, highly abrasive materials and why in many cases they are better alternatives to pads, tapes and foils.
Technical Library | 2016-06-30 14:00:32.0
When designing PLLs in nanometer CMOS, it is essential to validate the closed-loop PLL performance metrics with nanometer SPICE accuracy before going to silicon. Transistor-level, closed-loop PLL verification has been impractical due to traditional SPICE and RF simulator performance and capacity limitations. By using Analog FastSPICE, designers dont have to trade accuracy for performance. Read this white paper to see how AFS: Delivers closed-loop PLL transistor-level verification Supports direct jitter measurements Produces phase noise results correlating within 1-2dB of silicon
