Technical Library | 2024-08-29 18:30:46.0
The mechanical experience of consumption (i.e., feel, softness, and texture) of many foods is intrinsic to their enjoyable consumption, one example being the habit of twisting a sandwich cookie to reveal the cream. Scientifically, sandwich cookies present a paradigmatic model of parallel plate rheometry in which a fluid sample, the cream, is held between two parallel plates, the wafers. When the wafers are counterrotated, the cream deforms, flows, and ultimately fractures, leading to separation of the cookie into two pieces. We introduce Oreology (/Oriːˈɒl@dʒi/), from the Nabisco Oreo for "cookie" and the Greek rheo logia for "flow study," as the study of the flow and fracture of sandwich cookies. Using a laboratory rheometer, we measure failure mechanics of the eponymous Oreo's "creme" and probe the influence of rotation rate, amount of creme, and flavor on the stress–strain curve and postmortem creme distribution. The results typically show adhesive failure, in which nearly all (95%) creme remains on one wafer after failure, and we ascribe this to the production process, as we confirm that the creme-heavy side is uniformly oriented within most of the boxes of Oreos. However, cookies in boxes stored under potentially adverse conditions (higher temperature and humidity) show cohesive failure resulting in the creme dividing between wafer halves after failure. Failure mechanics further classify the creme texture as "mushy." Finally, we introduce and validate the design of an open-source, three-dimensionally printed Oreometer powered by rubber bands and coins for encouraging higher precision home studies to contribute new discoveries to this incipient field of study
Technical Library | 2007-11-01 17:16:07.0
This paper discusses micro-filled epoxy-based conducting adhesives modified with nanoparticles, conducting polymers, and low melting point (LMP) fillers for z-axis interconnections, especially as they relate to package level fabrication, integration,
Technical Library | 2009-01-01 16:37:38.0
Recent technology advancement has enabled enhancement in PWB electrical performance and wiring density. These innovations have taken the form of improved materials, novel PWB interconnect structures, and manufacturing technology. One such advancement is Z-axis conductive interconnect. The Z-interconnect technology involves building mini-substrates of 2 or 3 layers each, then assembling several mini-substrates together using conductive paste.
Technical Library | 2020-07-02 13:29:37.0
Industry standards such as J-STD-005 and JIS Z 3284-1994 call for the use of viscosity measurement(s) as a quality assurance test method for solder paste. Almost all solder paste produced and sold use a viscosity range at a single shear rate as part of the pass-fail criteria for shipment and customer acceptance respectively. As had been reported many times, an estimated 80% of the defects associated with the surface mount technology process involve defects created during the printing process. Viscosity at a single shear rate could predict a fatal flaw in the printability of a solder paste sample. However, false positive single shear rate viscosity readings are not unknown.
Technical Library | 2021-01-03 19:24:52.0
Reflow soldering is the primary method for interconnecting surface mount technology (SMT) applications. Successful implementation of this process depends on whether a low defect rate can be achieved. In general, defects often can be attributed to causes rooted in all three aspects, including materials, processes, and designs. Troubleshooting of reflow soldering requires identification and elimination of root causes. Where correcting these causes may be beyond the reach of manufacturers, further optimizing the other relevant factors becomes the next best option in order to minimize the defect rate.
Technical Library | 2008-02-26 15:02:19.0
More and more chip packages need multi-GHz RF structures to meet their performance targets. The ideal chip package needs to combine RF features with Digital features for these applications. They drive low-loss, controlled impedance transmission lines, flexibility in assigned signal and power layers, and clearances of various shapes in power layers. Building these features in a chip package is difficult without making the stack-up very thick or compromising the reliability of the product. In the present paper, we have designed and built a flip-chip package test vehicle (TV) to make new RF structures, using Z-axis interconnection (Zinterconnect) building blocks.
Technical Library | 2008-02-05 22:48:55.0
This study investigates the technological properties of quaternary or quinary alloys made by addition Bi or Bi and Sb elements to the SnAgCu solders. The influence of added elements on the electrical and mechanical properties of solder joints created by these solders between PCB and electronic components were evaluated.
Unipress - Institute of High Pressure Physics of the Polish Academy of Sciences
Technical Library | 2017-05-04 17:35:01.0
Most of today's printed circuit board base materials are anisotropic and it is not possible to use a simple method to measure thermal conductivity along the different axis, especially when a good accuracy is expected. Few base material suppliers' datasheet show X, Y and Z thermal conductivities. In most cases, a single value is given, moreover determined with a generic methodology, and not necessarily adapted to the reality of glass-reinforced composites with a strong anisotropy.After reminding of the fundamentals in thermal science, this paper gives an overview of the state-of the art in terms of thermal conductivity measurement on PCB base materials, and some typical values. It finally proposes an innovative method called transient fin method, and associated test sample, to perform reliable and consistent in plane thermal conductivity measurement on anisotropic PCB base materials.
Technical Library | 1999-08-09 11:36:27.0
Shrinking process technologies and increasing design sizes continually challenge design methodologies and EDA tools to develop at an ever-increasing rate. Before the complexities of deep submicron (DSM), gate and transistor delays dominated interconnect delays, and enabled simplified design methodologies that could focus on device analysis. The advent of DSM processes is changing all of this, invalidating assumptions and approximations that existing design methodologies are based upon, and forcing design teams to re-tool. High-capacity parasitic extraction tools are now critical for successful design tape-outs.
Technical Library | 2014-03-06 19:04:07.0
Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.
