Industry News | 2014-06-22 19:12:37.0
MIRTEC, “The Global Leader in Inspection Technology,” will exhibit in Booth #5444-1 at SEMICON West 2014, scheduled to take place July 8-10 at the Moscone Center in San Francisco, CA.
Industry News | 2003-02-25 09:10:01.0
The CSPEMI400 complements California Micro Devices' broad portfolio of CSP (chip scale package) devices for stand-alone ESD protection and EMI filter arrays with ESD protection, making it the most extensive in the industry.
Industry News | 2003-06-25 12:40:26.0
to manufacture and market printed circuit boards utilizing PCB Channel Routing technology from Nortel Networks
Industry News | 2007-01-29 15:10:05.0
Palo Alto, Calif.
Industry News | 2013-11-21 18:07:17.0
The company has demonstrated an unrivaled ability to understand the complexity of electronics assembly as well as key customer needs
Industry News | 2010-04-10 02:07:54.0
IPC has released the E revision of IPC J-STD-001, Requirements for Soldered Electrical and Electronic Assemblies. Recognized worldwide as the sole industry-consensus standard for soldering processes and materials, IPC J-STD-001E encompasses advanced technologies and provides new and updated criteria for all three classes of construction as well as expanded support for lead-free manufacturing.
Industry News | 2020-02-18 14:13:29.0
Michael Ford, Dale Lee, Joe O’Neil and S. Manian Ramkumar honored for their on-going leadership in IPC and the electronics industry
Industry News | 2013-01-30 17:54:43.0
Design, assembly, inspection and repair personnel have a new tool to help improve reliability of ball grid arrays (BGAs) and fine-pitch ball grid arrays (FBGAs) in high density applications, thanks to the newly released C revision of IPC-7095, Design and Assembly Process Implementation for BGAs.
Industry News | 2009-06-11 12:25:44.0
Company Expands Training Services
Industry News | 2011-12-14 15:35:33.0
Manufacturing processes, handling and printed circuit assembly (PCA) test can put a lot of mechanical stresses on packages, causing failures. As grid array packages get larger, identifying how to set safe levels for these steps becomes more difficult. A new quantitative test methodology within IPC/JEDEC-9707, Spherical Bend Test Method for Characterization of Board Level Interconnects, lets users determine how much strain packages can take before reliability degradation.
