Method of Modeling Differential Vias Method of Modeling Differential Vias Accurate, models for vias in a multilayer circuit board are necessary to predict link performance in the GHz regime. This paper describes a methodology to build a high
SMTnet Express March 7, 2013, Subscribers: 26214, Members: Companies: 13311, Users: 34412 PTH Core-to-Core Interconnect Using Sintered Conductive Pastes The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias
SMTnet Express, February 19, 2015, Subscribers: 22,404, Members: Companies: 14,224, Users: 37,735 Numerical Study on New Pin Pull Test for Pad Cratering Of PCB Billy Hu, Jesus Tan - Flextronics Pad cratering is an important failure mode besides
The Morphology Evolution and Voiding of Solder Joints on QFN Central Pads with a Ni/Au Finish SMTnet Express October 19, 2012, Subscribers: 25598, Members: Companies: 9011, Users: 33828 The Morphology Evolution and Voiding of Solder Joints on QFN
SMTnet Express, October 29, 2015, Subscribers: 23,683, Members: Companies: 14,724, Users: 39,236 Novel Approaches for Minimizing Pad Cratering Chen Xu, Yunhu Lin; Alcatel-Lucent, Yuan Zeng, Pericles A. Kondos; Unovis-Solutions.; Alcatel
