Industry News | 2011-01-18 13:46:21.0
Time and again, a major challenge lies in attaching integrated circuits (ICs) to highly integrated circuit board substrates in a space-saving manner. Würth Elektronik took this challenge on and found an ideal solution with the ESC (encapsulated solder connection) process. The chips are soldered and at the same time glued 'face-down" in their exact position.
Industry News | 2010-09-27 23:01:06.0
Christopher Associates/Koki Solder announces that Jasbir Bath will present a paper titled “An Investigation into the Development of Lead-Free Solder Paste for Package on Package (PoP) Component Manufacturing Applications” at the upcoming SMTAI Technical Conference, scheduled to take place October 25-28, 2010 at the Walt Disney World Swan and Dolphin Resort in Orlando, FL.
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2015-09-23 22:08:32.0
A molded interconnect device (MID) is an injection molded thermoplastic substrate which incorporates a conductive circuit pattern and integrates both mechanical and electrical functions. (...) Flip chip bonding of bare die on MID can be employed to fully utilize MID’s advantage in device miniaturization. Compared to the traditional soldering process, thermo-compression bonding with gold stud bumps provides a clear advantage in its fine pitch capability. However, challenges also exist. Few studies have been made on thermocompression bonding on MID substrate, accordingly little information is available on process optimization, material compatibility and bonding reliability. Unlike solder reflow, there is no solder involved and no “self-alignment,” therefore the thermo-compression bonding process is significantly more dependent on the capability of the machine for chip assembly alignment.
Heller Industries Inc. | https://hellerindustries.com/wp-content/uploads/2022/06/Vacuum-Fluxless-Reflow-Technology-for-Fine-Pitch.pdf
. The formic acid vapor reduces tin oxides on the surfaces of the bumps to its elemental state. Thus, the formic acid vapor takes the place of conventional fluxes
Surface Mount Technology Association (SMTA) | https://www.smta.org/knowledge/proceedings_abstract.cfm?PROC_ID=4722
), the Ag3Sn precipitate morphology and on the mechanical properties of micro Cu pillar bumps were examined. The shear strength performance of micro Cu pillars with three different bump diameters (30µm, 50µm, and 100µm) was also evaluated
