Electronics Forum | Thu Jan 06 08:03:47 EST 2005 | davef
On solder in vias: It looks like the via are not solder masked well and pick-up solder either: * Solder coating ... OR * During leveling It's possible that the design specifies openings in the solder mask for these via. On solder in the unsupporte
Electronics Forum | Thu Nov 22 12:56:12 EST 2001 | tony_sauve
Thanks for the comments & suggestions. Here's some info garnered from a telecon w/the PCB Fab house: -the blind via's extend from layer 2-17...this was a revelation. The info from our customer was that the via's only extended down 2 layers. Did I men
Industry News | 2009-03-05 15:12:58.0
ITASCA, IL � March 2009 � Kester is proud to announce that Peter Biocca and David Scheiner will hold a technical session titled �PCB Metalization� at the upcoming APEX Conference and Exhibition. Biocca, Kester's Senior Market Development Engineer, will be the moderator at the conference, which is scheduled to take place on Wednesday, April 1, from 10:15�11:45 a.m. in the South Pacific room.
This video describes what the IPC-J-STD-001 training program and the document for assembling printed circuit boards. In this video BEST Inc describes the assembly standard and what it entails . It also describes what the training program is. Operato
SMTnet Express, June 27, 2019, Subscribers: 32,092, Companies: 10,819, Users: 24,882 Advanced Cu Electroplating Process for Any Layer Via Fill Applications with Thin Surface Copper Credits: MacDermid Inc. Copper-filled micro-vias are a key
SMTnet Express, July 18, 2019, Subscribers: 32,162, Companies: 10,836, Users: 24,951 Via Fill and Through Hole Plating Process with Enhanced TH Microdistribution Credits: MacDermid Inc. The increased demand for electronic devices in recent years
Surface Mount Technology Association (SMTA) | https://www.smta.org/knowledge/proceedings_abstract.cfm?PROC_ID=5255
) European Union Directive has significantly reduced the use of tin/lead surface finishes for component terminations. A reexamination of solder joint wetting of lead-free solders with the new component terminations is key to establishing thermal process profiles that ensure acceptable solder joint integrity
| https://www.eptac.com/blog/are-voids-in-solder-joints-really-an-issue
? Posted on 5st June, 2012 by Mark Pilkington Well I’ve got to say it again, what is wrong with the existence of voids in solder joints
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