Technical Library: electromigration (Page 1 of 3)

Design of Experimentation for Affordability

Technical Library | 2019-07-11 11:07:08.0

Affordability is not exactly the primary word which comes to mind when discussing the use of design of experiments (DOE) principles, but is generally accepted as a necessary part of the engineering activities required in the development of a product or process. However, a number of studies have indicated that the cost savings derived from a well deliberated experimental design can be substantial in the initial stages where the conditions or parameters of a process are determined. Some studies have shown a greater than 50% cost savings compared to the more conventional means of trial and error approaches to process development. At ACI Technologies (ACI), we have found the use of DOE techniques fundamental in eliminating extraneous costs otherwise spent on unnecessary testing.

ACI Technologies, Inc.

The Quality and Reliability of Intel's Quarter Micron Process

Technical Library | 1999-05-07 08:48:52.0

This paper describes how the quality and reliability of Intel's products are designed, measured, modeled, and maintained. Four main reliability topics: ESD protection, electromigration, gate oxide wearout, and the modeling and management of mechanical stresses are discussed. Based on an analysis of the reliability implications of device scaling, we show how these four topics are of prime importance to component reliability...

Intel Corporation

Electromigration Damage Mechanics of Lead-Free Solder Joints Under Pulsed DC: A Computational Model

Technical Library | 2013-06-13 15:31:24.0

Electromigration (EM) is a mass transportation mechanism driven by electron wind force, thermal gradient, chemical potential and stress gradient. According to Moore’s law, number of transistors on integrated circuits (ICs) doubles approximately every 2 years. Moore’s law holds true since its introduction in 1970s. This insatiable demand for smaller ICs size, larger integration and higher Input/Output (IO) count of microelectronics has made ball grid array (BGA) the most promising connection type in electronic packaging industry. This trend, however, renders EM reliability of solders joints a major bottleneck to hinder further development of electronics industry...

Electronic Packaging Laboratory, State University of New York

DOE for Process Validation Involving Numerous Assembly Materials and Test Methods.

Technical Library | 2010-03-18 14:02:03.0

Selecting products that have been qualified by industry standards for use in printed circuit board assembly processes is an accepted best practice. That products which have been qualified, when used in combinations not specifically qualified, may have resultant properties detrimental to assembly function though, is often not adequately understood. Printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks, when qualified per industry standards, are qualified using very specific test methods which may not adequately mimic the assembly process ultimately used.

Trace Laboratories

Accurate Quantitative Physics-of-Failure Approach to Integrated Circuit Reliability

Technical Library | 2011-06-02 15:49:09.0

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs, ADCs, and memory. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit boa

DfR Solutions

Overview of Quality and Reliability Issues in the National Technology Roadmap for Semiconductors

Technical Library | 1999-08-05 10:27:43.0

This document is an update to the 1994 Quality and Reliability Roadmap issued in support of the 1994 National Technology Roadmap for Semiconductors. This report revisits the challenges, constraints, priorities, and research needs pertaining to quality and reliability issues. It also provides key project proposals that must be implemented to address concerns about reliability attainment and defect learning. An expanded section on test-to-test, diagnostics, and failure analysis; an edited version of the Product Analysis Forum Roadmap; and an appendix containing a draft report highlighting reliability issues is included.

SEMATECH

Thermal Engineering Overview.

Technical Library | 1999-05-06 12:00:47.0

The present problem with cooling microprocessors is a relatively new issue -- about 4 years old. It stems from the collision of two conflicting trends -- end-user desire for more powerful microprocessors to run the next generation software, and the equally strong demand for smaller, more mobile computer form factors. With each, the introduction of faster next-generation semiconductors aimed at improving computing power, heat concentration problems increase.

Aavid Thermalloy, LLC

Leaded and Lead-Free Solder Paste Evaluation Screening Procedure

Technical Library | 2010-05-12 16:21:05.0

Numerous studies have shown that greater than 60% of end of line defects in SMT assembly can be traced to solder paste and the printing process. Reflowing adds another 15% or so. In light of this fact, it is surprising that no simplified procedure for solder paste evaluation has been documented. This paper is about such a procedure.

Indium Corporation

Parasitic Extraction for Deep Submicron and Ultra-deep Submicron Designs

Technical Library | 1999-08-09 11:36:27.0

Shrinking process technologies and increasing design sizes continually challenge design methodologies and EDA tools to develop at an ever-increasing rate. Before the complexities of deep submicron (DSM), gate and transistor delays dominated interconnect delays, and enabled simplified design methodologies that could focus on device analysis. The advent of DSM processes is changing all of this, invalidating assumptions and approximations that existing design methodologies are based upon, and forcing design teams to re-tool. High-capacity parasitic extraction tools are now critical for successful design tape-outs.

Cadence Design Systems, Inc.

Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for High Performance Flip Chip Package

Technical Library | 2018-01-17 22:47:02.0

Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. (...) In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published. Originally published in the SMTA International 2016

STATS ChipPAC Inc

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