Technical Library | 2019-08-29 13:04:55.0
The true integration of electronics into textiles requires the fabrication of devices directly on the fibre itself using high-performance materials that allow seamless incorporation into fabrics. Woven electronics and opto-electronics, attained by intertwined fibres with complementary functions are the emerging and most ambitious technological and scientific frontier. Here we demonstrate graphene-enabled functional devices directly fabricated on textile fibres and attained by weaving graphene electronic fibres in a fabric. Capacitive touch-sensors and light-emitting devices were produced using a roll-to-roll-compatible patterning technique, opening new avenues for woven textile electronics. Finally, the demonstration of fabric-enabled pixels for displays and position sensitive functions is a gateway for novel electronic skin, wearable electronic and smart textile applications.
University of Exeter, College of Engineering, Mathematics and Physical Sciences
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
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