Electronics Forum | Thu Jun 16 08:31:15 EDT 2005 | jh0n!
The most part I have the most difficulty with is a 16mil QFN. We found that reducing stencil thickness to 4mil, and reducing aperatures for the IC by 20%, and setting local fiducials to the IC helped immensely. We used to get 75% or more bridged ou
Electronics Forum | Mon Oct 14 10:53:28 EDT 2013 | emeto
0.5 if you use electroformed stencil or > 0.8 if you use laser cut. 2. Always use fresh paste 3. Uses the right printer parameters for your paste(for example Alpha likes fast release of the stencil from the board - in DEK this is called separation s
Electronics Forum | Fri Jun 09 15:41:59 EDT 2006 | shawnvike
That is the problem I am having! Except with 3 separate manufacturers. To answer some of the other questions... Baking - diligence Stencil - as far as we can tell it is good Placement is good We are using Pb-free parts and solder, but I have see
Electronics Forum | Fri Jun 09 05:18:07 EDT 2006 | Rob
Hi Shawn, that you're baking the components makes me think that they are either old, or have been sitting around for a while (or none of the above & you are really dilligent!) Whilst baking will sort out the MSD issues (such as popcorning) it will
Electronics Forum | Mon Sep 29 11:44:39 EDT 2008 | manishc
We r facing less soder problem with qfp,using 4 mil tencil and lead free paste,tried out different combinations of reflow profile,can anybody suggest?
Electronics Forum | Wed Sep 18 06:53:05 EDT 2002 | CH
1) For solder short, pls check the paste height. Too much vol will cause short. For 15 mils use 5 mils thickness stencil if possible. Check profile preheat time to prevent hot slumpof the paste. 2) type 4 powder will be better for 15 mils pit
Electronics Forum | Wed Nov 06 15:47:49 EST 2002 | bpan
Hello All, Having a problem during reflow and would like your opinions. We are using Kester r562 water soluble paste and I am using a Kic 2000 profiler in a 4 zone oven (top only). We are seeing poor wetting or fillets that are not "passable" per IPC
Electronics Forum | Tue Dec 21 16:47:15 EST 1999 | GERARDIN
Hello Pascal As mentioned by Wolfgang the key issue is the printing process capability. For a thick copper level 90�m we noticed that the pad reduction can be greater than 20% depending on supplier sources. Typicaly for a cad Width = 0.4 we can
Electronics Forum | Wed Sep 18 18:41:17 EDT 2002 | davef
People have made good comments. Additional points are: * Your bridging is probably being caused by one or more of the following: [1] printing too much paste, [2] smearing the paste during placement or subsequent handling, or [3] paste slump during t
Electronics Forum | Tue Jan 08 09:23:18 EST 2013 | lock_2002
This is a question regarding soldermask between pins of fine pitch devices. The majority of our production designs end up with at least 2-3 mils of copper thickness on the external layers due to blind vias, wrap plating requirements, etc. Our curre
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