Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 2023-09-07 14:38:31.0
A repeat customer specializing in high-technology interconnect, sensor, and antenna solutions, partnered with us to dispense small volumes of solder paste (Indium 10.1 SAC305 T6SG 78%m) onto backplane connectors – gold pads 0.175mm x 0.225mm. We performed a test requiring 0.200mm diameter or smaller dots to demonstrate the dispensing capability required.
Technical Library | 2023-09-07 14:54:10.0
A global manufacturer of a broad line of electronic interconnect solutions worked with us to dispense conductive adhesive EpoTek H20E-FC. EpoTek H20E-FC is a two-component, electrically conductive, snap curing epoxy for photovoltaic thin film module stringing, semiconductor packaging and PCB circuit assembly. The primary goal was filling a rectangular cavity on a connector. The epoxy needed to fill the connector to the top of the walls in less than three seconds.
Technical Library | 2021-01-03 19:24:52.0
Reflow soldering is the primary method for interconnecting surface mount technology (SMT) applications. Successful implementation of this process depends on whether a low defect rate can be achieved. In general, defects often can be attributed to causes rooted in all three aspects, including materials, processes, and designs. Troubleshooting of reflow soldering requires identification and elimination of root causes. Where correcting these causes may be beyond the reach of manufacturers, further optimizing the other relevant factors becomes the next best option in order to minimize the defect rate.
Technical Library | 2010-03-23 11:50:22.0
This document discuss how to design SMT stencil base on IPC-7525. Introduction: PCBA (Printed Circuit Board Assembly) is a segment of printed circuit board technology. This segment of printed circuit board industry is concentrated in assemble all the pieces of electronic industry to one piece before output them to market. This segment covers: interconnection technology, package design technology, system integration technology, board and system test technology
Technical Library | 2019-08-19 09:46:13.0
Boundary scan is a method for testing interconnects on printed circuit boards (PCBs) or sub-blocks inside an integrated circuit. It has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and integrated circuit (IC) level access capabilities of boundary scan, its use has expanded beyond traditional board test applications into product design and service.
Technical Library | 2019-06-04 10:19:46.0
Interconnection technology relies very heavily on the ability of the conductors on a printed wiring assembly to maintain reliable signal integrity. Harsh environmental factors can precipitate a loss of conductivity due to oxidation and corrosion. Connections are typically soldered or inserted using pressure fitted connectors to obtain enough surface contact to meet the electrical conductivity requirements. In pressure contacts, surface integrity is especially critical where the abrasive effects of retraction and insertion can wear off the metallic finish from the contact area. This can expose the underlying copper or nickel and lead to increased resistance at the contact points. These types of conductors are frequently found in card edge connectors where the terminations are plated with a layer of nickel and gold (frequently referred to as gold fingers). A hard gold is typically used containing very small amounts of nickel and cobalt to increase the wear resistance.
Technical Library | 2019-10-16 10:20:25.0
A major goal of the development of advanced packaging technology is to reduce the size, weight, and power consumption of electronics components using state-of-the-art commercial technologies. One of the novel concepts involves the use of all three spatial dimensions when designing and producing new systems. In the past, electronic structures tended to be two dimensional in nature. Generally speaking, individually packaged integrated circuit (IC) dies were interconnected on printed circuit boards. Techniques such as die and package stacking naturally contribute to a reduction of the spatial footprint of any given electronic system design.
Technical Library | 2012-12-17 22:05:22.0
Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.
Technical Library | 2015-09-03 18:06:11.0
While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease of manufacture and the interconnection reliability are being reduced. This paper will introduce the use of embedded fibers in the interconnections as a means of addressing these issues.
