Technical Library | 2020-02-26 23:24:02.0
Shielding electronic systems against electromagnetic interference (EMI) has become a hot topic. Technological advancements toward 5G standards, wireless charging of mobile electronics, in-package antenna integration, and system-inpackage (SiP) adoption are driving the need to apply more effective EMI shielding and isolation to component packages and larger modules. For conformal shielding, EMI shielding materials for exterior package surfaces have mostly been applied with a physical vapor deposition (PVD) process of sputtering, leveraging front-end packaging technologies to back-end packaging applications. However, sputtering technology challenges in scalability and cost along with advancements in dispensable materials are driving considerations for alternative dispensing techniques for EMI shielding.
Technical Library | 2021-06-15 15:17:33.0
Shielding electronic systems against electromagnetic interference (EMI) has become a hot topic. Technological advancements toward 5G standards, wireless charging of mobile electronics, in-package antenna integration, and system-in-package (SiP) adoption are driving the need to apply more effective EMI shielding and isolation to component packages and larger modules. For conformal shielding, EMI shielding materials for exterior package surfaces have mostly been applied with a physical vapor deposition (PVD) process of sputtering, leveraging front-end packaging technologies to back-end packaging applications. However, sputtering technology challenges in scalability and cost along with advancements in dispensable materials are driving considerations for alternative dispensing techniques for EMI shielding.
Technical Library | 2011-11-10 18:06:17.0
With the advent of larger packages and higher densities/pitch the Industry has been concerned with the coplanarity of both the substrate package and the PCB motherboard. The iNEMI PCB Coplanarity WG generated a snapshot in time of the dynamic coplanarity
Technical Library | 2018-09-10 08:44:08.0
Issue: Moisture and bubbles in your dispensing material with larger quantities Solution: Scheugenpflug’s 55-gal Barrel Agitator Station Barrel agitators for casting resins take their technology from the paint sector. They fall short of meeting the special demands of the auto, medical, aeronautics and electronics industries. They can’t guarantee a solid seal on the barrels – often containing expensive, moisture sensitive resins – allowing the humidity of the surrounding environment to damage the material. Also, conventional barrel agitators, as opposed to smaller units, cannot work in a vacuum to process materials directly.
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
Technical Library | 2013-09-22 02:52:56.0
The PCB-assembly industry in constantly changing. Smaller footprints, new types of components and larger and more complex designs are accompanied by constant competitive pressures. As a result, electronics manufacturers need to continuously adapt their processes and make sure they exploit every opportunity for efficiency gains. This is the only way to improve quality and time to market and to increase profitability.
Technical Library | 1999-07-20 10:35:30.0
Circuit simulation is a necessary everyday tool to circuit designers who need to constantly verify and debug their circuits during the design process. As engineers face larger, more complex designs and tighter project schedules, fast SPICE simulation with no loss in accuracy has become a necessity. Simulation indeed accounts for a large portion of the time spent in the design and optimization of a new circuit...
Technical Library | 2010-02-10 23:50:23.0
The electronics industry has recently undertaken the transition to lead-free processing as a direct consequence of the RoHS directive, which came into force in July 2006. However, this is unlikely to be the last transition required since the European Solvent Emissions Directive, 1999 is starting to be implemented and enforced by national governments. This is resulting in pressure on larger manufacturers, currently emitting more than 5 tonnes of solvent vapour per annum to take steps to limit and reduce their emissions.
Technical Library | 2022-08-17 01:21:54.0
Back in the "good old days," stencil cleaning was effortless and effective. CFC-based solvents were sprayed or wiped onto a stencil with apertures hundreds of times larger than modern-day components. The stencil cleaning process was not considered a value-added procedure; instead it was the cleaning of a production tool. How times have changed. The late-1980s ushered in the end of most of the popular solvents, and the machines that consumed them. Assemblers turned to alternative cleaning agents, including IPAs and other solvents.
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
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