Technical Library | 2021-12-16 01:48:41.0
Package-on-Package (PoP) technology is widely used in mobile devices due to its simple design, lower cost and faster time to market. Warpage characteristic and requirement of PoP package becomes critical to ensure both the top and bottom package can be mounted with minimal yield lost. With this challenge in placed, iNEMI has been working relentlessly to fingerprint the current PoP package technology warpage characteristic and to establish some key learning for packaging technologies. The work also extended to understand the basic requirement needed for successful PoP stacking by analyzing the warpage data obtained and formulate a simple analytical equation to explain the true warpage requirement for PoP packaging.
Technical Library | 2019-04-17 21:29:14.0
Electroless nickel electroless palladium immersion gold (ENEPIG) surface finish for printed circuit board (PCB) has now become a key surface finish that is used for both tin-lead and lead-free solder assemblies. This paper presents the reliability of land grid array (LGA) component packages with 1156 pads assembled with tin-lead solder onto PCBs with an ENEPIG finish and then subjected to thermal cycling and then isothermal aging.
Technical Library | 2013-01-31 18:43:15.0
There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices, the emergence of lead-free processing, and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide. First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2014-08-19 15:39:13.0
Understanding warpage of package attach locations on PCBs under reflow temperature conditions is critical in surface mount technology. A new industry standard, IPC 9641, addresses this topic directly for the first time as an international standard.This paper begins by summarizing the sections of the IPC 9641 standard, including, measurement equipment selection, test setup and methodology, and accuracy verification. The paper goes further to discuss practical implementation of the IPC 9641 standards. Key advantages and disadvantages between available warpage measurement methods are highlighted. Choosing the correct measurement technique depends on requirements for warpage resolution, data density, measurement volume, and data correlation. From industry experience, best practice recommendations are made on warpage management of PCB land areas, covering how to setup, run, analyze, and report on local area PCB warpage.The release of IPC 9641 shows that flatness over temperature of the package land area on the PCB is critical to the SMT industry. Furthermore, compatibility of shapes between attaching surfaces in SMT, like a package and PCB, will be critical to product yield and quality in years to come.
Technical Library | 2014-03-06 19:04:07.0
Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.
Technical Library | 2021-08-11 01:00:37.0
Conformal coatings and potting materials continue to create issues for the electronics industry. This webinar will dig deeper into the failure modes of these materials, specifically issues with Coefficient of Thermal Expansion (CTE), delamination, cracking, de-wetting, pinholes/bubbles and orange peel issues with conformal coatings and what mitigation techniques are available. Similarly, this webinar will look at the failure modes of potting materials, (e.g Glass Transition Temperature (Tg), PCB warpage, the effects of improper curing and potential methods for correcting these situations.
Technical Library | 2014-08-19 16:04:28.0
SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller, with denser interconnect arrays, and processes such package-on-package assembly become prevalent, advanced methods using dual surface full-field data become critical for effective Assembly Planning, Quality Assurance, and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required, to effectively address the challenges of modern SMT assembly.
Technical Library | 2021-05-13 16:03:25.0
Sn-based lead-free solders such as Sn-Ag-Cu, Sn-Cu, and Sn-Bi have been used extensively for a long time in the electronic packaging field. Recently, low-temperature Sn-Bi solder alloys attract much attention from industries for flexible printed circuit board (FPCB) applications. Low melting temperatures of Sn-Bi solders avoid warpage wherein printed circuit board and electronic parts deform or deviate from the initial state due to their thermal mismatch during soldering. However, the addition of alloying elements and nanoparticles Sn-Bi solders improves the melting temperature, wettability, microstructure, and mechanical properties. Improving the brittleness of the eutecticSn-58wt%Bi solder alloy by grain refinement of the Bi-phase becomes a hot topic. In this paper, literature studies about melting temperature, microstructure, inter-metallic thickness, and mechanical properties of Sn-Bi solder alloys upon alloying and nanoparticle addition are reviewed
Technical Library | 2017-10-16 15:03:32.0
The miniaturization and advancement of electronic devices have been the driving force of design, research and development, and manufacturing in the electronic industry. However, there are some issues occurred associated with the miniaturization, for examples, warpage and reliability issues. In order to resolve these issues, a lot of research and development have been conducted in the industry and university with the target of moderate melting temperature solder alloys such as m.p. 280°C. These moderate temperature alloys have not resolve these issues yet due to the various limitations. YINCAE has been working on research and development of the materials with lower temperature soldering for higher temperature application. To meet this demand, YINCAE has developed solder joint encapsulant paste to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. This solder joint encapsulant paste can be used in typical lead-free profile and after reflow the application temperature can be up to over 300C, therefore it also eliminates red glue for double side reflow process. In this paper, we will discuss the reliability such as strength of solder joints, drop test performance and thermal cycling performance using this solder joint encapsulant paste in detail.
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