Technical Library | 2019-07-10 23:36:14.0
Pockets of gas, or voids, trapped in the solder interface between discrete power management devices and circuit assemblies are, unfortunately, excellent insulators, or barriers to thermal conductivity. This resistance to heat flow reduces the electrical efficiency of these devices, reducing battery life and expected functional life time of electronic assemblies. There is also a corresponding increase in current density (as the area for current conduction is reduced) that generates additional heat, further leading to performance degradation.
Technical Library | 2015-06-22 16:39:47.0
Surface finishing is an integral part of any PCB fabrication. It is generally applied to exposed Cu connectors and conductors on the board. Surface finishing has numerous important functions. It serves as a protective layer for the Cu connectors during storage. The surface finish helps minimize or reduce tarnish of the Cu substrate. Additionally, since it is the layer that comes into contact with other components during assembly, it ensures good solderability between the PCB and the component during assembly. Furthermore after assembly, the finish helps prolong the integrity of the solder joint during use. A general review of common PCB surface finishes is presented. The advantages and disadvantages of each are discussed and compared.
Technical Library | 2019-02-20 16:35:24.0
The High Density Packaging (HDP) User Group has completed a project evaluating the high frequency loss impacts of a variety of imaged core surface treatments (bond enhancement treatments, including chemical bonding and newer low etch alternative oxides) applied just prior to press lamination. Initial high frequency Dk/Df electrical test results did not show a strong correlation with any of the methods utilized within this project to measured surface roughness. The more significant factor affecting the measured loss is the choice of pre-lamination surface treatment. Most of the new chemical treatment systems outperform the older existing systems which depend upon surface roughness techniques to promote adhesion.
Technical Library | 2019-10-16 23:18:15.0
Despite being a continuous subject of discussion, the existence of voids and their effect on solder joint reliability has always been controversial. In this work we revisit previous works on the various types of voids, their origins and their effect on thermo-mechanical properties of solder joints. We focus on macro voids, intermetallics micro voids, and shrinkage voids, which result from solder paste and alloy characteristics. We compare results from the literature to our own experimental data, and use fatigue-crack initiation and propagation theory to support our findings. Through a series of examples, we show that size and location of macro voids are not the primary factor affecting solder joint mechanical and thermal fatigue life. Indeed, we observe that when these voids area conforms to the IPC-A-610 (D or F) or IPC-7095A standards, macro voids do not have any significant effect on thermal cycling or drop shock performance.
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