Technical Library: mm accept

Advances in Conductive Inks across Multiple Applications and Deposition Platforms

Technical Library | 2012-12-27 14:35:29.0

Printed Electronics is generally defined as the patterning of electronic materials, in solution form, onto flexible substrates, omitting any use of the photolithography, etching, and plating steps commonly found within the Printed Circuit Board (PCB) industry. The origins of printed electronics go back to the 1960s, and close variants of several original applications and market segments remain active today. Through the 1980s and 1990s Printed Electronic applications based on Membrane Touch Switch and Electroluminescent lighting technologies became common, and the screen printed electronic materials used then have formed the building blocks for many of the current and emerging technologies and applications... First published in the 2012 IPC APEX EXPO technical conference proceedings.


Environmentally Certified Technologies: A Case Study

Technical Library | 2000-06-21 17:55:59.0

There was once a time when precision cleaning required minimal thought. Just about anything that was dirty could be placed inside a vapor degreaser and emerge clean and dry in a matter of minutes. Today, precision cleaning decisions are seemingly endless with ever-changing environmental regulations, user safety issues and product compatibility concerns. Technologies range from spray-in-atmosphere to ultrasonics to spray under immersion using aqueous, solvent or semiaqueous chemistries. Which method works and with what chemistry? Will the process be safe or even allowed by the regulating agencies?

Smart Sonic Stencil Cleaning Systems

Corrosion Resistance of Different PCB Surface Finishes in Harsh Environments

Technical Library | 2012-08-09 20:33:45.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. Corrosion resistance is becoming one of the most important topics in the electronics industry. Corrosion results in field failures and huge losses, which annually total several bi


Investigation of Cutting Quality and Mitigation Methods for Laser Depaneling of Printed Circuit Boards

Technical Library | 2019-09-11 23:33:04.0

There are numerous techniques to singulate printed circuit boards after assembly including break-out, routing, wheel cutting and now laser cutting. Lasers have several desirable advantages such as very narrow kerf widths as well as virtually no dust, no mechanical stress, visual pattern recognition and fast set-up changes. The very narrow kerf width resulting from laser ablation and the very tight tolerance of the cutting path placement allows for more usable space on the panel. However, the energy used in the laser cutting process can also create unwanted products on the cut walls as a result of the direct laser ablation. The question raised often is: What are these products, and how far can the creation of such products be mitigated through variation of the laser cutting process, laser parameters and material handling? This paper discusses the type and quantity of the products found on sidewalls of laser depaneled circuit boards and it quantifies the results through measurements of breakdown voltage, as well as electrical impedance. Further this paper discusses mitigation strategies to prevent or limit the amount of change in surface quality as a result of the laser cutting process. Depending on the final application of the circuit board it may prompt a need for proper specification of the expected results in terms of cut surface quality. This in turn will impact the placement of runs and components during layout. It will assist designers and engineers in defining these parameters sufficiently in order to have a predictable quality of the circuit boards after depaneling.

LPKF Laser & Electronics

Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish

Technical Library | 2012-12-13 21:20:05.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4.

Samsung Electro-Mechanics

Material Effects of Laser Energy When Processing Circuit Board Substrates during Depaneling

Technical Library | 2017-04-27 17:10:16.0

Using modern laser systems for the depanelization of circuit boards can create some challenges for the production engineer when it is compared to traditional mechanical singulation methods. Understanding the effects of the laser energy to the substrate material properly is essential in order to take advantage of the technology without creating unintended side effects. This paper presents an in-depth analysis of the various laser system operating parameters that were performed to determine the resulting substrate material temperature changes. A theoretical model was developed and compared to actual measurements. The investigation includes how the temperature increase resulting from laser energy during depaneling affects the properties of the PCB substrate, which varies from no measurable change to a lowering of the surface resistance of the cut wall depending on the cutting parameters.

LPKF Laser & Electronics

Multilayer Ceramic Capacitors: Mitigating Rising Failure Rates

Technical Library | 2018-12-05 14:52:23.0

The multilayer ceramic capacitor (MLCC) has become a widely used electronics component both for surface mount and embedded PCB applications. The MLCC technologies have gone through a number of material and process changes such as the shift from precious metal electrode (PME) configurations which were predominantly silver/palladium to base metal electrodes (BME) dominated by nickel. Each of these changes were accompanied by both quality and reliability problems. The MLCC industry is now in the midst of an unprecedented set of challenges similar to the Moore’s Law challenges being faced by the semiconductor industry. While capacitor failures have historically been responsible for a significant percentage of product field failures (most estimates are ~30%) we are seeing disturbing developments in the low voltage (

DfR Solutions

Effect of Silicone Conformal Coating on Surface Insulation Resistance (SIR) For Printed Circuit Board Assemblies

Technical Library | 2013-04-18 16:46:42.0

Conformal coatings are considered a method of providing corrosion protection to electrical assemblies used in high-humidity or harsh environments. They are applied to PCBs for various reasons: to protect from moisture and contamination, to minimize dendritic growth, to provide stress relief, and for insulation resistance. These contribute to more durable handling, enhanced device reliability, and reduced warranty costs. Increased miniaturization of new circuit board designs requires flexible, low stress coating material to protect delicate components and fine-pitch leads. Silicone conformal coatings offer many advantages that address the general trend of ongoing PCBs designs, such as: high flexibility and low modulus to reduce stress on delicate or small components... First published in the 2012 IPC APEX EXPO technical conference proceedings.

Dow Corning Corporation

Stress Analysis and Optimization of a Flip Chip on Flex Electronic Packaging Method for Functional Electronic Textiles

Technical Library | 2020-12-24 02:50:56.0

A method for packaging integrated circuit silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm×8 mm× 0.53 mm and 2 mm×2 mm×0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three underfill adhesives (EP30AO, EP37-3FLF, and Epo-Tek 301 2fl), three highly flexible adhesives (Loctite 4860, Loctite 480, and Loctite 4902), and three substrates (Kapton,Mylar, and PEEK) have been evaluated, and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, was identified as the best materials combination with the optimum underfill and substrate thickness identified as 0.05 mm.

University of Southampton

Advanced Second Level Assembly Analysis Techniques - Troubleshooting Head-In-Pillow, Opens, and Shorts with Dual Full-Field 3D Surface Warpage Data Sets/

Technical Library | 2014-08-19 16:04:28.0

SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller, with denser interconnect arrays, and processes such package-on-package assembly become prevalent, advanced methods using dual surface full-field data become critical for effective Assembly Planning, Quality Assurance, and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required, to effectively address the challenges of modern SMT assembly.


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