Technical Library | 2012-04-26 18:52:37.0
First presented at IPC Apex Expo 2012. The reliability, as tested by thermal cycling, of printed wire boards (PWB) are established by three variables; copper quality, material robustness and design. The copper quality was most influential and could be eva
Technical Library | 2012-05-31 18:01:31.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. Considering technological advances in multi-depth cavities in the PCB manufacturing industry, various subtopics have materialized regarding the processing and application of such
Technical Library | 2015-04-02 20:12:58.0
The demands on volume delivery and positioning accuracy for solder paste deposits are increasing as the size and complexity of circuits continue to develop in the electronics industry. According to the iNEMI 2013 placement accuracy for these kinds of components will reach 6 sigma placement accuracy in X and Y of 30 um by 2023.This study attempts to understand the dependencies on piezo actuation pulse profile on jetting deposit quality, especially focused on positioning, satellites and shape. The correlation of deposit diameter and positioning deviation as a function of piezo actuation profile shows that positioning error for deposits increase almost monotonically with decreasing droplet volume irrespective of the piezo-actuation profile. The trends for shape and satellite levels are not as clear and demand further study.
Technical Library | 2012-10-11 19:50:09.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper shows the benefits by using a pure palladium Layer in the ENEPIG (Electroless Nickel, Electroless Palladium, Immersion Gold) and ENEP (Electroless Nickel, Electroless P
Technical Library | 2012-06-15 00:43:47.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. The world of spring-loaded test probes and special probes for in-circuit and functional tests have grown tremendously over the past few years. Ever increasing demands for electro
Technical Library | 2012-08-16 22:38:05.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. The physical mechanisms behind tin whisker formation in pure tin (Sn) films continue to elude the microelectronics industry. Despite modest advances in whisker mitigation techniqu
Technical Library | 2013-05-02 12:45:25.0
Summary of some new and existing technologies for printed electronics outside of traditional membrane switch manufacturing. Discussion of requirements for understanding the technology of these applications in order to capitalize on them... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2012-01-05 18:40:07.0
Conformal coating is applied to circuit cards to provide a dielectric layer on an electronic board. This layer functions as a membrane between the board and the environment. With this coating in place, the circuit card can withstand more moisture by incre
Technical Library | 2012-05-31 23:35:31.0
Industrial network security solutions essential to today's PLC - SCADA security. Lack of security on an industrial network could cause a serious threat to the system, to the personnel involved in it, in fact, production machines networks without proper se
Technical Library | 2013-03-14 17:19:28.0
Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings.
