Technical Library | 2019-06-11 09:34:37.0
Recently ACI Technologies was asked to perform failure analysis on a hermetically sealed transistor for potential electrostatic discharge (ESD) or electrostatic overstress (EOS). ACI was asked to determine if the field-failed transistor was damaged by ESD or EOS. In order to properly assess the failure, additional samples were requested.
Technical Library | 2012-12-14 14:28:20.0
This paper examines the potential failure mechanisms that can damage modern lowvoltage CMOS devices and their relationship to electrical testing. Failure mechanisms such as electrostatic discharge (ESD), CMOS latch-up, and transistor gate oxide degradation can occur as a result of electrical over-voltage stress (EOS). In this paper, EOS due to electrical testing is examined and an experiment is conducted using pulsed voltage waveforms corresponding to conditions encountered during in-circuit electrical testing. Experimental results indicate a correlation between amplitude and duration of the pulse waveform and device degradation due to one or more of the failure mechanisms.
Technical Library | 2020-02-18 09:56:24.0
Glob Top, Dam and Fill & Flit Chip Underfill To protect PCBs from damaging outside influences, they are coated with a thin layer of casting resin or protective finish during the conformal coating process. In addition to sealing the entire circuit board, it is possible to pot only sections or individual components on the substrate. Different methods ranging from "glob top" to "dam and fill" and "flip chip underfill" have been developed for this purpose.
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