Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 1999-05-06 13:38:45.0
This paper traces the key steps that led to the invention of the integrated circuit (IC). The first part of this paper reviews the steady improvements in the performance and fabrication of single transistors in the decade after the Bell Labs breakthrough work in 1947. It sketches the various developments needed to produce a practical IC. In addition, the more advanced processes such as diffusion, oxide masking, photolithography, and epitaxy, which culminated in the planar process, are summarized.
Technical Library | 2015-05-21 18:46:31.0
In this work the reliability of an embedded planar capacitor laminate under temperature and voltage stress is investigated. The capacitor laminate consisted of an epoxy-BaTiO3 composite sandwiched between two layers of copper. The test vehicle with the embedded capacitors was subjected to a temperature of 125oC and a voltage bias of 200 V for 1000 hours. Capacitance, dissipation factor, and insulation resistance were monitored in-situ. Failed capacitors exhibited a sharp drop in insulation resistance, indicating avalanche breakdown. The decrease in the capacitance after 1000 hours was no more than 8% for any of the devices monitored. The decrease in the capacitance was attributed to delamination in the embedded capacitor laminate and an increase in the spacing between the copper layers.
Technical Library | 2021-07-06 21:13:36.0
The surface finishes commonly used on printed circuit boards (PCBs) have an effect on solder paste performance in the surface mount process. Some surface finishes are non-planar like hot air solder level (HASL) which can lead to inconsistencies in solder paste printing. Other surface finishes are difficult to wet during reflow like organic solderability preservative (OSP). What is the overall effect of surface finish on solder paste performance? Which solder paste is best for each surface finish? It is the goal of this paper to answer these questions.
Technical Library | 2014-03-06 19:04:07.0
Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.
Technical Library | 2021-05-06 13:45:49.0
The high-sensitive micro eddy-current testing (ECT) probe composed of planar meander coil as an exciter and spin-valve giant magneto-resistance (SV-GMR) sensor as a magnetic sensor for bare printed circuit board (PCB) inspection is proposed in this paper. The high-sensitive micro ECT probe detects the magnetic field distribution on the bare PCB and the image processing technique analyzes output signal achieved from the ECT probe to exhibit and to identify the defects occurred on the PCB conductor. The inspection results of the bare PCB model show that the proposed ECT probe with the image processing technique can be applied to bare PCB inspection. Furthermore, the signal variations are investigated to prove the possibility of applying the proposed ECT probe to inspect the high-density PCB that PCB conductor width and gap are less than 100 μm.
Technical Library | 2023-01-10 20:15:42.0
Over the past years there has been consistent growth in the use of electroless nickel / immersion gold (ENIG) as a final finish. The finish is now frequently being used for PBGA, CSP, QFP and COB and more recently gathered considerable interest as a low cost under-bump metallization for flip chip bumping application. One of the largest users for this finish has been the telecommunication industry, were millions of square meters of PCBs with ENIG have been successfully used. The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via thermal integrity. In addition the nickel layer offers advantages such as co-planarity, Al-wire bondability and the use as contact surface for keypads or contact switching. Especially those pads, which are not covered by solder need a protective coating in corrosive environment – such as high humidity or pollutant gas.
Technical Library | 2020-01-15 23:54:34.0
Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics.
Technical Library | 2020-07-22 19:39:05.0
The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures. Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable. The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for a reliable PWB. Minimum copper wrap plating thickness has become an even a bigger concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design. PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching. The companies started a project to study the relationship between Copper wrap plating thickness and via reliability. The project had two phases. This paper will present findings from both Phase 1 and Phase 2.
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