Electronics Forum | Mon Jun 17 21:33:20 EDT 2002 | davef
Ken, Yes, when quality is good, increasing throughput of a bottlenecked resource [lowering costs] is a fine goal. [Wouldn't E Goldratt smile?] In MY real world, quality is not as good as it should be. We have: * Suppliers that do not do as asked.
Electronics Forum | Thu Jun 13 11:30:41 EDT 2002 | davef
Most SMT lines are comprised of several pieces of equipment. Each piece of equipment, the components, the plant environment, and the people running the line can have / cause variations in their operation that each can affect product quality. Consid
Electronics Forum | Mon May 29 12:00:05 EDT 2006 | jbrower
Howdy Jack, That is a huge request, It would help if you start from the begining of your process and break down the problems that you are having.
Electronics Forum | Wed May 31 23:37:37 EDT 2006 | jacksaria
Hello EC, Thank you very much for the good input. I really appreciated. Our mounnters is Panasonic CM402,CM301. Do you have any suggestions/procedure how to reduce the sources of variance at each step of component placement process? regards,
Electronics Forum | Wed May 31 21:33:52 EDT 2006 | jacksaria
Hello jbrower, Thank you for the feedback. Actually, our main problems is the pick and throw. Whats your suggestion how to control the pick and throw?What are the factors that affecting pick and throw?How to reduce the sources of variance at each st
Electronics Forum | Thu Jun 01 04:51:21 EDT 2006 | EC
Hi TS, Most of the machines will face this problem after been using few years.....I handling SMT equipments ( Fuji machine ) and process.....sorry if I have offened you...... Hi Jack, Firstly, you must able to tell which component having a high thr
Electronics Forum | Mon Oct 05 06:08:02 EDT 2009 | pengliang
hello, I'm Pengliang,from China job in ASUS computer and working with smt process department.(so I hope to dicuss the process issue analyse and improvement) any issue pls. pass out . msn iD: liang.pung@hotmail.com good luck
Electronics Forum | Thu Mar 30 21:46:56 EST 2000 | Dave F
Reg: This is copy / paste from draft version of IPC 7095 ( issued May 1999 ) ... 7.3 Assembly accept/reject criteria 7.3.1 Voids in solder joint a. Sources of Voids There can be voids in solder balls, or at the solder joints to the BGA, or at the so
Electronics Forum | Fri Oct 12 11:18:57 EDT 2012 | srgbarba
Hi, I want to ask if someone saw the combo process at smt lines for panel array (bot & top per both sides), I just perform some experiments and it works perfectly, and I validate the T hus (Cg/Pa) and no one component were dropped after the 2nd reflo
Electronics Forum | Fri Jan 07 09:56:04 EST 2005 | davef
Electroformed stencil suppliers follow. The describe the stencil production process on their sites. * Aplpha Metals [ http://www.alphametals.com/products/ stencils/pdf/PG_Electroform_Stencils.pdf ] * Chepaume [ http://www.chepaume.com/electroforming
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