Technical Library | 2023-09-15 11:42:44.0
Discover our SMT cutting machine range for precise and efficient PCB assembly. Improve production speed and quality with cutting-edge technology.
Technical Library | 2023-09-18 03:40:02.0
Our SMT intelligent solder paste supply system is the perfect solution for businesses that need to improve the accuracy and consistency of their SMT paste printing. Our system uses the latest technology to automatically dispense the correct amount of solder paste to each stencil opening, ensuring that your SMT assemblies are consistently high-quality.
Technical Library | 2023-09-13 13:03:25.0
SMT auto aqueous stencil cleaning machines are an essential tool for any SMT production line. These machines use a variety of methods to remove contaminants and debris from SMT stencils, which can cause defects and reliability issues.
Technical Library | 2015-06-11 21:20:29.0
The use of bottom terminated components (BTC) has become widespread, specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type, improved electrical and thermal performance relative to older packaging technology, and low cost make the QFN/BTC attractive for many applications.Over the past 15 years, the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design, and must be given special attention to balance the dissimilar requirements
Technical Library | 2018-10-24 18:04:12.0
Polymer Thick Film (PTF)-based printed electronics (aka Printed Electronics) has improved in durability over the last few decades and is now a proven alternative to copper circuitry in many applications once thought beyond the capability of PTF circuitry. This paper describes peak performance and areas for future improvement.State-of-the-art PTF circuitry performance includes the ability to withstand sharp crease tests, 85C/85%RH damp heat 5VDC bias aging (silver migration), auto seat durability cycling, SMT mandrel flexing, and others. The IPC/SGIA subcommittee for Standards Tests development has adopted several ASTM test methods for PTF circuitry and is actively developing needed improvements or additions. These standards are described herein. Advantages of PTF circuitry over copper include: varied conductive material compositions, lower cost and lower environmental impact. Necessary improvements include: robust integration of chip and power, higher conductivity, and fine line multi-layer patterning.
Technical Library | 2019-02-27 15:23:47.0
A study was performed to investigate, evaluate and qualify new reworkable underfill materials to be used primarily with ball grid arrays (BGAs), Leadless SMT devices, QFNs, connectors and passive devices to improve reliability. The supplier of the sole source, currently used underfill, has indicated they may discontinue its manufacture in the near future. The current underfill material is used on numerous circuit card assemblies (CCAs) at several sites and across multiple programs/business areas. In addition, it is used by several of our contract CCA suppliers.The study objectives include evaluation of material properties for down select, dispensability and rework evaluation for further down select, accelerated life testing for final selection and qualification; and process development to implement into production and at our CCA suppliers. The paper will describe the approach used, material property test results and general findings relative to process characteristics and rework ability.
Technical Library | 2013-11-21 12:01:11.0
Previous experimentation on a highly miniaturized and densely populated SMT assembly revealed the optimum stencil alloy and flux-repellent coating for its stencil printing process. Production implementation of the materials that were identified in the study resulted in approximately 5% print yield improvement across all assemblies throughout the operation, validating the results of the initial tests. A new set of studies was launched to focus on the materials themselves, with the purpose of optimizing their performance on the assembly line (...) Results of the prior tests are reviewed, and the new test vehicle, experimental setup and results are presented and discussed.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
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