Technical Library: use and scale and on and conformal and coating (Page 1 of 2)

Managing the transition on a global scale -- changing the cleaning agent means changes to equipment, processes, process control specifications and standards.

Technical Library | 1999-05-09 12:36:40.0

The production of electronics began with hand soldering, followed by manual cleaning, which reached its peak during the NASA program. Each step in the process tended to be considered on a stand alone basis, without thought being given to the preceding and following steps. Since each step had its own set of specifications, this led to a "patchwork" approach to overall quality.


The Effect of Coating and Potting on the Reliability of QFN Devices.

Technical Library | 2014-08-28 17:09:23.0

The fastest growing package types in the electronics industry today are Bottom Termination Components (BTCs). While the advantages of BTCs are well documented, they pose significant reliability challenges to users. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies. This is especially true for new component packaging like BTCs. Obtaining relevant information can be difficult since information is often segmented and the focus is on design opportunities not on reliability risks (...)Commonly used conformal coating and potting processes have resulted in shortened fatigue life under thermal cycling conditions. Why do conformal coating and potting reduce fatigue life? This paper details work undertaken to understand the mechanisms underlying this reduction. Verification and determination of mechanical properties of some common materials are performed and highlighted. Recommendations for material selection and housing design are also given.

DfR Solutions

Conformal Surface Plasmons Propagating on Ultrathin and Flexible Films

Technical Library | 2013-09-05 17:44:14.0

Surface plasmon polaritons (SPPs) are localized surface electromagnetic waves that propagate along the interface between a metal and a dielectric. Owing to their inherent subwavelength confinement, SPPs have a strong potential to become building blocks of a type of photonic circuitry built up on 2D metal surfaces; however, SPPs are difficult to control on curved surfaces conformably and flexibly to produce advanced functional devices. Here we propose the concept of conformal surface plasmons (CSPs), surface plasmon waves that can propagate on ultrathin and flexible films to long distances in a wide broadband range from microwave to mid-infrared frequencies.

Southeast University (SEU)

Effects of Tin and Copper Nanotexturization on Tin Whisker Formation

Technical Library | 2012-08-16 22:38:05.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. The physical mechanisms behind tin whisker formation in pure tin (Sn) films continue to elude the microelectronics industry. Despite modest advances in whisker mitigation techniqu

Johns Hopkins Applied Physics Laboratory

Wire Bonding and Soldering on Enepig and Enep Surface Finishes with Pure Pd-Layers

Technical Library | 2012-10-11 19:50:09.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper shows the benefits by using a pure palladium Layer in the ENEPIG (Electroless Nickel, Electroless Palladium, Immersion Gold) and ENEP (Electroless Nickel, Electroless P


Assembly and Reliability of 1704 I/O FCBGA and FPBGAs

Technical Library | 2013-03-14 17:19:28.0

Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings.

Jet Propulsion Laboratory

Packaging Technology and Design Challenge for Fine Pitch Micro-Bump Cu-Pillar and BOT (Direct Bond on Substrate-Trace) Using TCNCP

Technical Library | 2015-12-02 18:32:50.0

(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.

Altera Corporation


Technical Library | 2015-12-15 19:45:22.0


Rent-A-Geek, LLC

Screen and Stencil Printing Processes for Wafer Backside Coating

Technical Library | 2009-09-09 15:08:19.0

Stencil printing equipment has traditionally been used in the surface mount assembly industry for solder paste printing. In recent years the flexibility of the tool has been exploited for a wide range of materials and processes to aid semiconductor packaging and assembly. One such application has been the deposition of adhesive coatings onto the backside of silicon wafers.

ASM Assembly Systems (DEK)

New development of atomic layer deposition: processes, methods and applications

Technical Library | 2020-09-08 16:43:32.0

Atomic layer deposition (ALD) is an ultra-thin film deposition technique that has found many applications owing to its distinct abilities. They include uniform deposition of conformal films with controllable thickness, even on complex three-dimensional surfaces, and can improve the efficiency of electronic devices. This technology has attracted significant interest both for fundamental understanding how the new functional materials can be synthesized by ALD and for numerous practical applications, particularly in advanced nanopatterning for microelectronics, energy storage systems, desalinations, catalysis and medical fields. This review introduces the progress made in ALD, both for computational and experimental methodologies, and provides an outlook of this emerging technology in comparison with other film deposition methods. It discusses experimental approaches and factors that affect the deposition and presents simulation methods, such as molecular dynamics and computational fluid dynamics, which help determine and predict effective ways to optimize ALD processes, hence enabling the reduction in cost, energy waste and adverse environmental impacts. Specific examples are chosen to illustrate the progress in ALD processes and applications that showed a considerable impact on other technologies.

University of Johannesburg

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