Technical Library | 1999-05-07 10:14:57.0
This paper describes a model developed to calculate number of redundant good die per wafer. A block redundancy scheme is used here, where the entire defective memory subarray is replaced by a redundant element. A formula is derived to calculate the amount of improvement expected after redundancy. This improvement is given in terms of the ratio of the overall good die per wafer to the original good die per wafer after considering some key factors.
Technical Library | 1999-08-09 11:09:42.0
Organic Solderability Preservatives (OSPs), also known as anti-tarnish, on bare copper printed circuit boards (PCBs) are becoming more prevalent in the electronics industry as the low-cost replacement to Hot Air Solder Leveling (HASL). Introducing the anti-tarnish alternative into the customer sites requires working closely with the coating supplier, assembler, and Original Equipment Manufacturer (OEM) to gain a mutual understanding of respective processing concerns and finished product requirements.
Technical Library | 2008-05-07 17:54:58.0
Tracking goods through manufacturing was originally accomplished with pencil, paper and human input. Barcodes introduced an automated, machine-readable tracking mechanism that streamlined all types of manufacturing. But modern printed circuit board (PCB) assemblies are running into limitations because of barcode labels. And though barcodes and RFID tags will co-exist, the relatively large barcode labels have to find increasingly scarce real estate on high density boards.
Technical Library | 2009-04-30 18:06:24.0
This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.
Technical Library | 2015-05-11 21:27:52.0
Originating from the last millenium, almost three decades ago, the introduction of surface mount packaging triggered a wave of changes throughout many aspects of electronics production. A small number of talented, innovative test engineers from various big players of the industry started to attend meetings to discuss the impact of that change of technology on their future test concepts for modern assemblies. The Joint Test Action Group was born.
Technical Library | 2023-06-12 16:52:47.0
The technological advancement of component and PCB technology from through-hole to surface mount (SMT) is a major factor in the miniaturization of today's electronics. Smaller and smaller component sizes and more densely packed PCBs lead to more powerful designs in much smaller product packages. With advancement, however, comes a new set of challenges in building these smaller, more complex assemblies. This is the challenge original equipment manufacturers (OEM) and contract manufacturers (CM) face today.
Technical Library | 2017-02-16 16:53:49.0
This experiment considers the reliability of a variety of different electronic components and evaluates them on 0.200” power computing printed circuit boards with OSP. Single-sided assemblies were built separately for the Top-side and Bottom-side of the boards. This data is for boards on the FR4-06 substrate.This paper was originally published by SMTA in the Proceedings of SMTA International.
Technical Library | 2023-11-20 17:36:58.0
With PCB complexity and density increasing and also wider use of 3D devices, tougher requirements are now imposed on device inspection both during original manufacture and at their subsequent processing onto printed circuit boards. More complicated and dense packages have more opportunities to exhibit defects both internal to the package as well as to the PCB. As components increase in complexity their cost increases, making counterfeiting them a potentially lucrative business for unscrupulous individuals and organizations.
Technical Library | 2019-08-15 13:31:52.0
Cracks in ceramic chip capacitors can be introduced at any process step during surface mount assembly. Thermal shock has become a "pat" answer for all of these cracks, but about 75 to 80% originate from other sources. These sources include pick and place machine centering jaws, vacuum pick up bit, board depanelization, unwarping boards after soldering, test fixtures, connector insulation, final assembly, as well as defective components. Each source has a unique signature in the type of crack that it develops so that each can be identified as the source of error.
Technical Library | 2021-12-16 01:33:11.0
Ball Grid Array devices, BGAs, are widely used in a vast range of products including consumer, telecommunications and office based systems. As an area array device of solder joints, it provides high packing density with a relatively easy introduction cycle. However, over the last couple of years engineers have started to experiment, and in some cases implement, stacked packages, of the type often called Package on Package, or POP. In simple terms, POP devices are the stacking of components, one on top of the other, either during the original component manufacture or during printed board assembly.
